| Message ID | 20240509021531.680920-1-samuel.holland@sifive.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | perf vendor events riscv: Update SiFive CPU PMU events | expand |
On Wed, May 08, 2024 at 07:14:53PM -0700, Samuel Holland wrote: > This series updates the PMU event JSON files to add support for newer > SiFive CPUs, including those used in the upcoming HiFive Premier P550 > board. Since most changes are incremental, symbolic links are used when > a set of events is unchanged from the previous CPU series. Ian, are you ok with this? Someone with such systems can provide some Tested-by? - Arnaldo > > Eric Lin (5): > perf vendor events riscv: Update SiFive Bullet events > perf vendor events riscv: Add SiFive Bullet version 0x07 events > perf vendor events riscv: Add SiFive Bullet version 0x0d events > perf vendor events riscv: Add SiFive P550 events > perf vendor events riscv: Add SiFive P650 events > > Samuel Holland (2): > perf vendor events riscv: Rename U74 to Bullet > perf vendor events riscv: Remove leading zeroes > > tools/perf/pmu-events/arch/riscv/mapfile.csv | 6 +- > .../cycle-and-instruction-count.json | 12 +++ > .../arch/riscv/sifive/bullet-07/firmware.json | 1 + > .../riscv/sifive/bullet-07/instruction.json | 1 + > .../arch/riscv/sifive/bullet-07/memory.json | 1 + > .../riscv/sifive/bullet-07/microarch.json | 62 +++++++++++++ > .../riscv/sifive/bullet-07/watchpoint.json | 42 +++++++++ > .../cycle-and-instruction-count.json | 1 + > .../arch/riscv/sifive/bullet-0d/firmware.json | 1 + > .../riscv/sifive/bullet-0d/instruction.json | 1 + > .../arch/riscv/sifive/bullet-0d/memory.json | 1 + > .../riscv/sifive/bullet-0d/microarch.json | 72 +++++++++++++++ > .../riscv/sifive/bullet-0d/watchpoint.json | 1 + > .../sifive/{u74 => bullet}/firmware.json | 0 > .../arch/riscv/sifive/bullet/instruction.json | 92 +++++++++++++++++++ > .../arch/riscv/sifive/bullet/memory.json | 32 +++++++ > .../arch/riscv/sifive/bullet/microarch.json | 57 ++++++++++++ > .../arch/riscv/sifive/p550/firmware.json | 1 + > .../arch/riscv/sifive/p550/instruction.json | 1 + > .../arch/riscv/sifive/p550/memory.json | 47 ++++++++++ > .../arch/riscv/sifive/p550/microarch.json | 1 + > .../p650/cycle-and-instruction-count.json | 1 + > .../arch/riscv/sifive/p650/firmware.json | 1 + > .../arch/riscv/sifive/p650/instruction.json | 1 + > .../arch/riscv/sifive/p650/memory.json | 57 ++++++++++++ > .../arch/riscv/sifive/p650/microarch.json | 62 +++++++++++++ > .../arch/riscv/sifive/p650/watchpoint.json | 1 + > .../arch/riscv/sifive/u74/instructions.json | 92 ------------------- > .../arch/riscv/sifive/u74/memory.json | 32 ------- > .../arch/riscv/sifive/u74/microarch.json | 57 ------------ > 30 files changed, 555 insertions(+), 182 deletions(-) > create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json > create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json > create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json > create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json > create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json > create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json > create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json > create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json > create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json > create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json > create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json > create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json > rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json (100%) > create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json > create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json > create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json > create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json > create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json > create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json > create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json > create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json > create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json > create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json > create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json > create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json > create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json > delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json > delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json > delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json > > -- > 2.44.0 >
This series updates the PMU event JSON files to add support for newer SiFive CPUs, including those used in the upcoming HiFive Premier P550 board. Since most changes are incremental, symbolic links are used when a set of events is unchanged from the previous CPU series. Eric Lin (5): perf vendor events riscv: Update SiFive Bullet events perf vendor events riscv: Add SiFive Bullet version 0x07 events perf vendor events riscv: Add SiFive Bullet version 0x0d events perf vendor events riscv: Add SiFive P550 events perf vendor events riscv: Add SiFive P650 events Samuel Holland (2): perf vendor events riscv: Rename U74 to Bullet perf vendor events riscv: Remove leading zeroes tools/perf/pmu-events/arch/riscv/mapfile.csv | 6 +- .../cycle-and-instruction-count.json | 12 +++ .../arch/riscv/sifive/bullet-07/firmware.json | 1 + .../riscv/sifive/bullet-07/instruction.json | 1 + .../arch/riscv/sifive/bullet-07/memory.json | 1 + .../riscv/sifive/bullet-07/microarch.json | 62 +++++++++++++ .../riscv/sifive/bullet-07/watchpoint.json | 42 +++++++++ .../cycle-and-instruction-count.json | 1 + .../arch/riscv/sifive/bullet-0d/firmware.json | 1 + .../riscv/sifive/bullet-0d/instruction.json | 1 + .../arch/riscv/sifive/bullet-0d/memory.json | 1 + .../riscv/sifive/bullet-0d/microarch.json | 72 +++++++++++++++ .../riscv/sifive/bullet-0d/watchpoint.json | 1 + .../sifive/{u74 => bullet}/firmware.json | 0 .../arch/riscv/sifive/bullet/instruction.json | 92 +++++++++++++++++++ .../arch/riscv/sifive/bullet/memory.json | 32 +++++++ .../arch/riscv/sifive/bullet/microarch.json | 57 ++++++++++++ .../arch/riscv/sifive/p550/firmware.json | 1 + .../arch/riscv/sifive/p550/instruction.json | 1 + .../arch/riscv/sifive/p550/memory.json | 47 ++++++++++ .../arch/riscv/sifive/p550/microarch.json | 1 + .../p650/cycle-and-instruction-count.json | 1 + .../arch/riscv/sifive/p650/firmware.json | 1 + .../arch/riscv/sifive/p650/instruction.json | 1 + .../arch/riscv/sifive/p650/memory.json | 57 ++++++++++++ .../arch/riscv/sifive/p650/microarch.json | 62 +++++++++++++ .../arch/riscv/sifive/p650/watchpoint.json | 1 + .../arch/riscv/sifive/u74/instructions.json | 92 ------------------- .../arch/riscv/sifive/u74/memory.json | 32 ------- .../arch/riscv/sifive/u74/microarch.json | 57 ------------ 30 files changed, 555 insertions(+), 182 deletions(-) create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json (100%) create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json