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[3/7] perf vendor events riscv: Update SiFive Bullet events

Message ID 20240509021531.680920-4-samuel.holland@sifive.com (mailing list archive)
State Handled Elsewhere
Headers show
Series perf vendor events riscv: Update SiFive CPU PMU events | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR success PR summary
conchuod/patch-3-test-1 success .github/scripts/patches/tests/build_rv32_defconfig.sh
conchuod/patch-3-test-2 success .github/scripts/patches/tests/build_rv64_clang_allmodconfig.sh
conchuod/patch-3-test-3 success .github/scripts/patches/tests/build_rv64_gcc_allmodconfig.sh
conchuod/patch-3-test-4 success .github/scripts/patches/tests/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-3-test-5 success .github/scripts/patches/tests/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-3-test-6 success .github/scripts/patches/tests/checkpatch.sh
conchuod/patch-3-test-7 success .github/scripts/patches/tests/dtb_warn_rv64.sh
conchuod/patch-3-test-8 success .github/scripts/patches/tests/header_inline.sh
conchuod/patch-3-test-9 success .github/scripts/patches/tests/kdoc.sh
conchuod/patch-3-test-10 success .github/scripts/patches/tests/module_param.sh
conchuod/patch-3-test-11 success .github/scripts/patches/tests/verify_fixes.sh
conchuod/patch-3-test-12 success .github/scripts/patches/tests/verify_signedoff.sh

Commit Message

Samuel Holland May 9, 2024, 2:14 a.m. UTC 
From: Eric Lin <eric.lin@sifive.com>

Regenerate the event lists from the original hardware description. This
makes them consistent with the event lists for newer versions of the
hardware, allowing most files to be reused across hardware versions.

Signed-off-by: Eric Lin <eric.lin@sifive.com>
Co-developed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

 .../arch/riscv/sifive/bullet/instruction.json | 44 +++++++++----------
 .../arch/riscv/sifive/bullet/memory.json      | 24 +++++-----
 .../arch/riscv/sifive/bullet/microarch.json   | 38 ++++++++--------
 3 files changed, 53 insertions(+), 53 deletions(-)
diff mbox series

Patch

diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
index d5c370f70819..284e4c1566e0 100644
--- a/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
@@ -2,91 +2,91 @@ 
   {
     "EventName": "EXCEPTION_TAKEN",
     "EventCode": "0x100",
-    "BriefDescription": "Exception taken"
+    "BriefDescription": "Counts exceptions taken"
   },
   {
     "EventName": "INTEGER_LOAD_RETIRED",
     "EventCode": "0x200",
-    "BriefDescription": "Integer load instruction retired"
+    "BriefDescription": "Counts integer load instructions retired"
   },
   {
     "EventName": "INTEGER_STORE_RETIRED",
     "EventCode": "0x400",
-    "BriefDescription": "Integer store instruction retired"
+    "BriefDescription": "Counts integer store instructions retired"
   },
   {
     "EventName": "ATOMIC_MEMORY_RETIRED",
     "EventCode": "0x800",
-    "BriefDescription": "Atomic memory operation retired"
+    "BriefDescription": "Counts atomic memory instructions retired"
   },
   {
     "EventName": "SYSTEM_INSTRUCTION_RETIRED",
     "EventCode": "0x1000",
-    "BriefDescription": "System instruction retired"
+    "BriefDescription": "Counts system instructions retired (CSR, WFI, MRET, etc.)"
   },
   {
     "EventName": "INTEGER_ARITHMETIC_RETIRED",
     "EventCode": "0x2000",
-    "BriefDescription": "Integer arithmetic instruction retired"
+    "BriefDescription": "Counts integer arithmetic instructions retired"
   },
   {
     "EventName": "CONDITIONAL_BRANCH_RETIRED",
     "EventCode": "0x4000",
-    "BriefDescription": "Conditional branch retired"
+    "BriefDescription": "Counts conditional branch instructions retired"
   },
   {
     "EventName": "JAL_INSTRUCTION_RETIRED",
     "EventCode": "0x8000",
-    "BriefDescription": "JAL instruction retired"
+    "BriefDescription": "Counts jump-and-link instructions retired"
   },
   {
     "EventName": "JALR_INSTRUCTION_RETIRED",
     "EventCode": "0x10000",
-    "BriefDescription": "JALR instruction retired"
+    "BriefDescription": "Counts indirect jump instructions (JALR) retired"
   },
   {
     "EventName": "INTEGER_MULTIPLICATION_RETIRED",
     "EventCode": "0x20000",
-    "BriefDescription": "Integer multiplication instruction retired"
+    "BriefDescription": "Counts integer multiplication instructions retired"
   },
   {
     "EventName": "INTEGER_DIVISION_RETIRED",
     "EventCode": "0x40000",
-    "BriefDescription": "Integer division instruction retired"
+    "BriefDescription": "Counts integer division instructions retired"
   },
   {
     "EventName": "FP_LOAD_RETIRED",
     "EventCode": "0x80000",
-    "BriefDescription": "Floating-point load instruction retired"
+    "BriefDescription": "Counts floating-point load instructions retired"
   },
   {
     "EventName": "FP_STORE_RETIRED",
     "EventCode": "0x100000",
-    "BriefDescription": "Floating-point store instruction retired"
+    "BriefDescription": "Counts floating-point store instructions retired"
   },
   {
-    "EventName": "FP_ADDITION_RETIRED",
+    "EventName": "FP_ADD_RETIRED",
     "EventCode": "0x200000",
-    "BriefDescription": "Floating-point addition retired"
+    "BriefDescription": "Counts floating-point add instructions retired"
   },
   {
-    "EventName": "FP_MULTIPLICATION_RETIRED",
+    "EventName": "FP_MUL_RETIRED",
     "EventCode": "0x400000",
-    "BriefDescription": "Floating-point multiplication retired"
+    "BriefDescription": "Counts floating-point multiply instructions retired"
   },
   {
-    "EventName": "FP_FUSEDMADD_RETIRED",
+    "EventName": "FP_MULADD_RETIRED",
     "EventCode": "0x800000",
-    "BriefDescription": "Floating-point fused multiply-add retired"
+    "BriefDescription": "Counts floating-point fused multiply-add instructions retired"
   },
   {
     "EventName": "FP_DIV_SQRT_RETIRED",
     "EventCode": "0x1000000",
-    "BriefDescription": "Floating-point division or square-root retired"
+    "BriefDescription": "Counts floating point divide or square root instructions retired"
   },
   {
     "EventName": "OTHER_FP_RETIRED",
     "EventCode": "0x2000000",
-    "BriefDescription": "Other floating-point instruction retired"
+    "BriefDescription": "Counts other floating-point instructions retired"
   }
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
index ba3168f8a4cd..70441a55dd66 100644
--- a/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
@@ -1,32 +1,32 @@ 
 [
   {
-    "EventName": "ICACHE_RETIRED",
+    "EventName": "ICACHE_MISS",
     "EventCode": "0x102",
-    "BriefDescription": "Instruction cache miss"
+    "BriefDescription": "Counts instruction cache misses"
   },
   {
-    "EventName": "DCACHE_MISS_MMIO_ACCESSES",
+    "EventName": "DCACHE_MISS",
     "EventCode": "0x202",
-    "BriefDescription": "Data cache miss or memory-mapped I/O access"
+    "BriefDescription": "Counts data cache misses"
   },
   {
-    "EventName": "DCACHE_WRITEBACK",
+    "EventName": "DCACHE_RELEASE",
     "EventCode": "0x402",
-    "BriefDescription": "Data cache write-back"
+    "BriefDescription": "Counts writeback requests from the data cache"
   },
   {
-    "EventName": "INST_TLB_MISS",
+    "EventName": "ITLB_MISS",
     "EventCode": "0x802",
-    "BriefDescription": "Instruction TLB miss"
+    "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests"
   },
   {
-    "EventName": "DATA_TLB_MISS",
+    "EventName": "DTLB_MISS",
     "EventCode": "0x1002",
-    "BriefDescription": "Data TLB miss"
+    "BriefDescription": "Counts Data TLB misses caused by data address translation requests"
   },
   {
     "EventName": "UTLB_MISS",
     "EventCode": "0x2002",
-    "BriefDescription": "UTLB miss"
+    "BriefDescription": "Counts Unified TLB misses caused by address translation requests"
   }
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
index 8036e72fb0d4..d9cdb7d747ee 100644
--- a/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
@@ -2,56 +2,56 @@ 
   {
     "EventName": "ADDRESSGEN_INTERLOCK",
     "EventCode": "0x101",
-    "BriefDescription": "Address-generation interlock"
+    "BriefDescription": "Counts cycles with an address-generation interlock"
   },
   {
-    "EventName": "LONGLAT_INTERLOCK",
+    "EventName": "LONGLATENCY_INTERLOCK",
     "EventCode": "0x201",
-    "BriefDescription": "Long-latency interlock"
+    "BriefDescription": "Counts cycles with a long-latency interlock"
   },
   {
-    "EventName": "CSR_READ_INTERLOCK",
+    "EventName": "CSR_INTERLOCK",
     "EventCode": "0x401",
-    "BriefDescription": "CSR read interlock"
+    "BriefDescription": "Counts cycles with a CSR interlock"
   },
   {
-    "EventName": "ICACHE_ITIM_BUSY",
+    "EventName": "ICACHE_BLOCKED",
     "EventCode": "0x801",
-    "BriefDescription": "Instruction cache/ITIM busy"
+    "BriefDescription": "Counts cycles in which the instruction cache was not able to provide an instruction"
   },
   {
-    "EventName": "DCACHE_DTIM_BUSY",
+    "EventName": "DCACHE_BLOCKED",
     "EventCode": "0x1001",
-    "BriefDescription": "Data cache/DTIM busy"
+    "BriefDescription": "Counts cycles in which the data cache blocked an instruction"
   },
   {
     "EventName": "BRANCH_DIRECTION_MISPREDICTION",
     "EventCode": "0x2001",
-    "BriefDescription": "Branch direction misprediction"
+    "BriefDescription": "Counts mispredictions of conditional branch direction (taken/not taken)"
   },
   {
     "EventName": "BRANCH_TARGET_MISPREDICTION",
     "EventCode": "0x4001",
-    "BriefDescription": "Branch/jump target misprediction"
+    "BriefDescription": "Counts mispredictions of the target PC of control-flow instructions"
   },
   {
-    "EventName": "PIPE_FLUSH_CSR_WRITE",
+    "EventName": "PIPELINE_FLUSH",
     "EventCode": "0x8001",
-    "BriefDescription": "Pipeline flush from CSR write"
+    "BriefDescription": "Counts flushes of the core pipeline. Common causes include fence.i and CSR accesses"
   },
   {
-    "EventName": "PIPE_FLUSH_OTHER_EVENT",
+    "EventName": "REPLAY",
     "EventCode": "0x10001",
-    "BriefDescription": "Pipeline flush from other event"
+    "BriefDescription": "Counts instruction replays"
   },
   {
-    "EventName": "INTEGER_MULTIPLICATION_INTERLOCK",
+    "EventName": "INTEGER_MUL_DIV_INTERLOCK",
     "EventCode": "0x20001",
-    "BriefDescription": "Integer multiplication interlock"
+    "BriefDescription": "Counts cycles with a multiply or divide interlock"
   },
   {
     "EventName": "FP_INTERLOCK",
     "EventCode": "0x40001",
-    "BriefDescription": "Floating-point interlock"
+    "BriefDescription": "Counts cycles with a floating-point interlock"
   }
-]
\ No newline at end of file
+]