[12/12] riscv: disable the EFI PECOFF header for M-mode

Message ID	20191028121043.22934-13-hch@lst.de (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=R/Cm=YV=lists.infradead.org=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B8BF921783 From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com> Subject: [PATCH 12/12] riscv: disable the EFI PECOFF header for M-mode Date: Mon, 28 Oct 2019 13:10:43 +0100 Message-Id: <20191028121043.22934-13-hch@lst.de> In-Reply-To: <20191028121043.22934-1-hch@lst.de> References: <20191028121043.22934-1-hch@lst.de> MIME-Version: 1.0 Precedence: list Cc: Anup Patel <anup@brainfault.org>, Damien Le Moal <damien.lemoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org
Series	[01/12] riscv: abstract out CSR names for supervisor vs machine mode \| expand [01/12] riscv: abstract out CSR names for supervisor vs machine mode [02/12] riscv: don't allow selecting SBI based drivers for M-mode [03/12] riscv: poison SBI calls for M-mode [04/12] riscv: cleanup the default power off implementation [05/12] riscv: implement remote sfence.i using IPIs [06/12] riscv: add support for MMIO access to the timer registers [07/12] riscv: provide native clint access for M-mode [08/12] riscv: read the hart ID from mhartid on boot [09/12] riscv: clear the instruction cache and all registers when booting [10/12] riscv: add nommu support [11/12] riscv: provide a flat image loader [12/12] riscv: disable the EFI PECOFF header for M-mode

Message ID

20191028121043.22934-13-hch@lst.de (mailing list archive)

State

New, archived

Headers

DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B8BF921783
From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>,
 Paul Walmsley <paul.walmsley@sifive.com>
Subject: [PATCH 12/12] riscv: disable the EFI PECOFF header for M-mode
Date: Mon, 28 Oct 2019 13:10:43 +0100
Message-Id: <20191028121043.22934-13-hch@lst.de>
In-Reply-To: <20191028121043.22934-1-hch@lst.de>
References: <20191028121043.22934-1-hch@lst.de>
MIME-Version: 1.0
Precedence: list
Cc: Anup Patel <anup@brainfault.org>, Damien Le Moal <damien.lemoal@wdc.com>,
 linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
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 linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org

Series

[01/12] riscv: abstract out CSR names for supervisor vs machine mode | expand

Commit Message

Christoph Hellwig Oct. 28, 2019, 12:10 p.m. UTC

No point in bloating the kernel image with a bootloader header if
we run bare metal.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/kernel/head.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 84a6f0a4b120..9bca97ffb67a 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -16,6 +16,7 @@ 
 
 __INIT
 ENTRY(_start)
+#ifndef CONFIG_RISCV_M_MODE
 	/*
 	 * Image header expected by Linux boot-loaders. The image header data
 	 * structure is described in asm/image.h.
@@ -47,6 +48,7 @@  ENTRY(_start)
 
 .global _start_kernel
 _start_kernel:
+#endif /* CONFIG_RISCV_M_MODE */
 	/* Mask all interrupts */
 	csrw CSR_IE, zero
 	csrw CSR_IP, zero

[12/12] riscv: disable the EFI PECOFF header for M-mode

Commit Message

Patch