[v2,9/9] riscv: defconfig: enable T-HEAD SoC

Message ID	20230518184541.2627-10-jszhang@kernel.org (mailing list archive)
State	Superseded
Delegated to:	Conor Dooley
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> From: Jisheng Zhang <jszhang@kernel.org> To: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org> Subject: [PATCH v2 9/9] riscv: defconfig: enable T-HEAD SoC Date: Fri, 19 May 2023 02:45:41 +0800 Message-Id: <20230518184541.2627-10-jszhang@kernel.org> In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 Precedence: list Cc: devicetree@vger.kernel.org, Yangtao Li <frank.li@vivo.com>, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Wei Fu <wefu@redhat.com> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	Add Sipeed Lichee Pi 4A RISC-V board support \| expand [v2,0/9] Add Sipeed Lichee Pi 4A RISC-V board support [v2,1/9] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC [v2,2/9] dt-bindings: timer: Add T-HEAD TH1520 clint [v2,3/9] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles [v2,4/9] dt-binding: riscv: add T-HEAD CPU reset [v2,5/9] riscv: Add the T-HEAD SoC family Kconfig option [v2,6/9] riscv: dts: add initial T-HEAD TH1520 SoC device tree [v2,7/9] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree [v2,8/9] MAINTAINERS: add entry for T-HEAD RISC-V SoC [v2,9/9] riscv: defconfig: enable T-HEAD SoC

Message ID

20230518184541.2627-10-jszhang@kernel.org (mailing list archive)

State

Superseded

Delegated to:

Conor Dooley

Headers

From: Jisheng Zhang <jszhang@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Guo Ren <guoren@kernel.org>
Subject: [PATCH v2 9/9] riscv: defconfig: enable T-HEAD SoC
Date: Fri, 19 May 2023 02:45:41 +0800
Message-Id: <20230518184541.2627-10-jszhang@kernel.org>
In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org>
References: <20230518184541.2627-1-jszhang@kernel.org>
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Precedence: list
Cc: devicetree@vger.kernel.org, Yangtao Li <frank.li@vivo.com>,
 linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
 Wei Fu <wefu@redhat.com>
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 linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org

Series

Add Sipeed Lichee Pi 4A RISC-V board support | expand

Context	Check	Description
conchuod/tree_selection	fail	Failed to apply to next/pending-fixes, riscv/for-next or riscv/master

Context

Check

Description

conchuod/tree_selection

fail

Failed to apply to next/pending-fixes, riscv/for-next or riscv/master

Enable T-HEAD SoC config in defconfig to allow the default upstream kernel to boot on Sipeed Lichee Pi 4A board. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+)

Comments

Conor Dooley May 18, 2023, 8:58 p.m. UTC | #1

On Fri, May 19, 2023 at 02:45:41AM +0800, Jisheng Zhang wrote:
> Enable T-HEAD SoC config in defconfig to allow the default
> upstream kernel to boot on Sipeed Lichee Pi 4A board.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  arch/riscv/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index d98d6e90b2b8..109e4b5b003c 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -27,6 +27,7 @@ CONFIG_EXPERT=y
>  CONFIG_PROFILING=y
>  CONFIG_SOC_MICROCHIP_POLARFIRE=y
>  CONFIG_ARCH_RENESAS=y
> +CONFIG_ARCH_THEAD=y
>  CONFIG_SOC_SIFIVE=y
>  CONFIG_SOC_STARFIVE=y
>  CONFIG_ARCH_SUNXI=y
> -- 
> 2.40.0
>

Palmer Dabbelt May 19, 2023, 8:56 p.m. UTC | #2

On Thu, 18 May 2023 11:45:41 PDT (-0700), jszhang@kernel.org wrote:
> Enable T-HEAD SoC config in defconfig to allow the default
> upstream kernel to boot on Sipeed Lichee Pi 4A board.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  arch/riscv/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index d98d6e90b2b8..109e4b5b003c 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -27,6 +27,7 @@ CONFIG_EXPERT=y
>  CONFIG_PROFILING=y
>  CONFIG_SOC_MICROCHIP_POLARFIRE=y
>  CONFIG_ARCH_RENESAS=y
> +CONFIG_ARCH_THEAD=y
>  CONFIG_SOC_SIFIVE=y
>  CONFIG_SOC_STARFIVE=y
>  CONFIG_ARCH_SUNXI=y

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

Guo Ren May 20, 2023, 1:16 a.m. UTC | #3

Acked-by: Guo Ren <guoren@kernel.org>

On Sat, May 20, 2023 at 4:56 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Thu, 18 May 2023 11:45:41 PDT (-0700), jszhang@kernel.org wrote:
> > Enable T-HEAD SoC config in defconfig to allow the default
> > upstream kernel to boot on Sipeed Lichee Pi 4A board.
> >
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> >  arch/riscv/configs/defconfig | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > index d98d6e90b2b8..109e4b5b003c 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -27,6 +27,7 @@ CONFIG_EXPERT=y
> >  CONFIG_PROFILING=y
> >  CONFIG_SOC_MICROCHIP_POLARFIRE=y
> >  CONFIG_ARCH_RENESAS=y
> > +CONFIG_ARCH_THEAD=y
> >  CONFIG_SOC_SIFIVE=y
> >  CONFIG_SOC_STARFIVE=y
> >  CONFIG_ARCH_SUNXI=y
>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index d98d6e90b2b8..109e4b5b003c 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -27,6 +27,7 @@  CONFIG_EXPERT=y
 CONFIG_PROFILING=y
 CONFIG_SOC_MICROCHIP_POLARFIRE=y
 CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_THEAD=y
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_ARCH_SUNXI=y

[v2,9/9] riscv: defconfig: enable T-HEAD SoC

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