| Message ID | 807f75e433a0f900da40ebb6a448349c98580072.1706577450.git.unicorn_wang@outlook.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 08573ba006ab7bc29c183e0b3c362a0b34f1d87b |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | riscv: sophgo: add reset support for SG2042 | expand |
LGTM Reviewed-by: Inochi Amaoto <inochiama@outlook.com> On Tue, Jan 30, 2024 at 09:50:51AM +0800, Chen Wang wrote: > From: Chen Wang <unicorn_wang@outlook.com> > > Add resets property for uart0 for completeness, although it is > deasserted by default. > > Signed-off-by: Chen Wang <unicorn_wang@outlook.com> > --- > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi > index eeb341e16bfd..81fda312f988 100644 > --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi > @@ -343,6 +343,7 @@ uart0: serial@7040000000 { > clock-frequency = <500000000>; > reg-shift = <2>; > reg-io-width = <4>; > + resets = <&rstgen RST_UART0>; > status = "disabled"; > }; > }; > -- > 2.25.1 >
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index eeb341e16bfd..81fda312f988 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -343,6 +343,7 @@ uart0: serial@7040000000 { clock-frequency = <500000000>; reg-shift = <2>; reg-io-width = <4>; + resets = <&rstgen RST_UART0>; status = "disabled"; }; };