Show patches with: Submitter = Rajnesh Kanwal       |    State = Action Required       |   52 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v3,6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs. target/riscv: Add support for Control Transfer Records Ext. - - - --- 2024-11-04 Rajnesh Kanwal New
[v3,5/6] target/riscv: Add CTR sctrclr instruction. target/riscv: Add support for Control Transfer Records Ext. - - - --- 2024-11-04 Rajnesh Kanwal New
[v3,4/6] target/riscv: Add support to record CTR entries. target/riscv: Add support for Control Transfer Records Ext. - - - --- 2024-11-04 Rajnesh Kanwal New
[v3,3/6] target/riscv: Add support for Control Transfer Records extension CSRs. target/riscv: Add support for Control Transfer Records Ext. - - - --- 2024-11-04 Rajnesh Kanwal New
[v3,2/6] target/riscv: Add Control Transfer Records CSR definitions. target/riscv: Add support for Control Transfer Records Ext. 1 - - --- 2024-11-04 Rajnesh Kanwal New
[v3,1/6] target/riscv: Remove obsolete sfence.vm instruction target/riscv: Add support for Control Transfer Records Ext. - 2 - --- 2024-11-04 Rajnesh Kanwal New
[v2,6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs. target/riscv: Add support for Control Transfer Records Ext. - - - --- 2024-06-19 Rajnesh Kanwal New
[v2,5/6] target/riscv: Add CTR sctrclr instruction. target/riscv: Add support for Control Transfer Records Ext. - - - --- 2024-06-19 Rajnesh Kanwal New
[v2,4/6] target/riscv: Add support to record CTR entries. target/riscv: Add support for Control Transfer Records Ext. - - - --- 2024-06-19 Rajnesh Kanwal New
[v2,3/6] target/riscv: Add support for Control Transfer Records extension CSRs. target/riscv: Add support for Control Transfer Records Ext. - - - --- 2024-06-19 Rajnesh Kanwal New
[v2,2/6] target/riscv: Add Control Transfer Records CSR definitions. target/riscv: Add support for Control Transfer Records Ext. 1 - - --- 2024-06-19 Rajnesh Kanwal New
[v2,1/6] target/riscv: Remove obsolete sfence.vm instruction target/riscv: Add support for Control Transfer Records Ext. - 2 - --- 2024-06-19 Rajnesh Kanwal New
[6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs. target/riscv: Add support for Control Transfer Records Ext. - - - --- 2024-05-29 Rajnesh Kanwal New
[5/6] target/riscv: Add CTR sctrclr instruction. target/riscv: Add support for Control Transfer Records Ext. - - - --- 2024-05-29 Rajnesh Kanwal New
[4/6] target/riscv: Add support to record CTR entries. target/riscv: Add support for Control Transfer Records Ext. - - - --- 2024-05-29 Rajnesh Kanwal New
[3/6] target/riscv: Add support for Control Transfer Records extension CSRs. target/riscv: Add support for Control Transfer Records Ext. - - - --- 2024-05-29 Rajnesh Kanwal New
[2/6] target/riscv: Add Control Transfer Records CSR definitions. target/riscv: Add support for Control Transfer Records Ext. - - - --- 2024-05-29 Rajnesh Kanwal New
[1/6] target/riscv: Remove obsolete sfence.vm instruction target/riscv: Add support for Control Transfer Records Ext. - 1 - --- 2024-05-29 Rajnesh Kanwal New
[v2,2/2] target/riscv: Move Guest irqs out of the core local irqs range. target/riscv: Minor fixes and improvements for Virtual IRQs 1 1 - --- 2024-05-20 Rajnesh Kanwal New
[v2,1/2] target/riscv: Extend virtual irq csrs masks to be 64 bit wide. target/riscv: Minor fixes and improvements for Virtual IRQs 1 1 - --- 2024-05-20 Rajnesh Kanwal New
[2/2] target/riscv: Move Guest irqs out of the core local irqs range. Minor fixes and improvements for Virtual IRQs - - - --- 2024-05-13 Rajnesh Kanwal New
[1/2] target/riscv: Extend virtual irq csrs masks to be 64 bit wide. Minor fixes and improvements for Virtual IRQs - 1 - --- 2024-05-13 Rajnesh Kanwal New
[v5,6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-16 Rajnesh Kanwal New
[v5,5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-16 Rajnesh Kanwal New
[v5,4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-16 Rajnesh Kanwal New
[v5,3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-16 Rajnesh Kanwal New
[v5,2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-16 Rajnesh Kanwal New
[v5,1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-16 Rajnesh Kanwal New
[v4,6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-12 Rajnesh Kanwal New
[v4,5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-12 Rajnesh Kanwal New
[v4,4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-12 Rajnesh Kanwal New
[v4,3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-12 Rajnesh Kanwal New
[v4,2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-12 Rajnesh Kanwal New
[v4,1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-12 Rajnesh Kanwal New
[v3,6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-11 Rajnesh Kanwal New
[v3,5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-11 Rajnesh Kanwal New
[v3,4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-11 Rajnesh Kanwal New
[v3,3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-11 Rajnesh Kanwal New
[v3,2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-11 Rajnesh Kanwal New
[v3,1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-10-11 Rajnesh Kanwal New
[v2,6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-05-26 Rajnesh Kanwal New
[v2,5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-05-26 Rajnesh Kanwal New
[v2,4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-05-26 Rajnesh Kanwal New
[v2,3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-05-26 Rajnesh Kanwal New
[v2,2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-05-26 Rajnesh Kanwal New
[v2,1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie. target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support - 1 - --- 2023-05-26 Rajnesh Kanwal New
[6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support. Add RISC-V Virtual IRQs and IRQ filtering support - - - --- 2023-05-18 Rajnesh Kanwal New
[5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support. Add RISC-V Virtual IRQs and IRQ filtering support - - - --- 2023-05-18 Rajnesh Kanwal New
[4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip. Add RISC-V Virtual IRQs and IRQ filtering support - - - --- 2023-05-18 Rajnesh Kanwal New
[3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled Add RISC-V Virtual IRQs and IRQ filtering support - - - --- 2023-05-18 Rajnesh Kanwal New
[2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. Add RISC-V Virtual IRQs and IRQ filtering support - - - --- 2023-05-18 Rajnesh Kanwal New
[1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie. Add RISC-V Virtual IRQs and IRQ filtering support - - - --- 2023-05-18 Rajnesh Kanwal New