[v6,67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs

From: Frank Chang <frank.chang@sifive.com>

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To: qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org
Subject: [PATCH v6 67/72] target/riscv: rvv-1.0: set mstatus.SD bit when
 writing vector CSRs
Date: Tue, 12 Jan 2021 17:39:41 +0800
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Cc: Frank Chang <frank.chang@sifive.com>,
 Alistair Francis <Alistair.Francis@wdc.com>,
 Palmer Dabbelt <palmer@dabbelt.com>,
 Sagar Karandikar <sagark@eecs.berkeley.edu>,
 Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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Message ID	20210112093950.17530-68-frank.chang@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=AIrx=GP=nongnu.org=qemu-devel-bounces+qemu-devel=archiver.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CBA3622D05 From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v6 67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs Date: Tue, 12 Jan 2021 17:39:41 +0800 Message-Id: <20210112093950.17530-68-frank.chang@sifive.com> In-Reply-To: <20210112093950.17530-1-frank.chang@sifive.com> References: <20210112093950.17530-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Cc: Frank Chang <frank.chang@sifive.com>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	support vector extension v1.0 \| expand [v6,00/72] support vector extension v1.0 [v6,01/72] target/riscv: drop vector 0.7.1 and add 1.0 support [v6,02/72] target/riscv: Use FIELD_EX32() to extract wd field [v6,03/72] target/riscv: rvv-1.0: add mstatus VS field [v6,04/72] target/riscv: rvv-1.0: add sstatus VS field [v6,05/72] target/riscv: rvv-1.0: introduce writable misa.v field [v6,06/72] target/riscv: rvv-1.0: add translation-time vector context status [v6,07/72] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers [v6,08/72] target/riscv: rvv-1.0: add vcsr register [v6,09/72] target/riscv: rvv-1.0: add vlenb register [v6,10/72] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers [v6,11/72] target/riscv: rvv-1.0: remove MLEN calculations [v6,12/72] target/riscv: rvv-1.0: add fractional LMUL [v6,13/72] target/riscv: rvv-1.0: add VMA and VTA [v6,14/72] target/riscv: rvv-1.0: update check functions [v6,15/72] target/riscv: introduce more imm value modes in translator functions [v6,16/72] target/riscv: rvv:1.0: add translation-time nan-box helper function [v6,17/72] target/riscv: rvv-1.0: configure instructions [v6,18/72] target/riscv: rvv-1.0: stride load and store instructions [v6,19/72] target/riscv: rvv-1.0: index load and store instructions [v6,20/72] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns [v6,21/72] target/riscv: rvv-1.0: fault-only-first unit stride load [v6,22/72] target/riscv: rvv-1.0: amo operations [v6,23/72] target/riscv: rvv-1.0: load/store whole register instructions [v6,24/72] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns [v6,25/72] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation [v6,26/72] target/riscv: rvv-1.0: floating-point square-root instruction [v6,27/72] target/riscv: rvv-1.0: floating-point classify instructions [v6,28/72] target/riscv: rvv-1.0: mask population count instruction [v6,29/72] target/riscv: rvv-1.0: find-first-set mask bit instruction [v6,30/72] target/riscv: rvv-1.0: set-X-first mask bit instructions [v6,31/72] target/riscv: rvv-1.0: iota instruction [v6,32/72] target/riscv: rvv-1.0: element index instruction [v6,33/72] target/riscv: rvv-1.0: allow load element with sign-extended [v6,34/72] target/riscv: rvv-1.0: register gather instructions [v6,35/72] target/riscv: rvv-1.0: integer scalar move instructions [v6,36/72] target/riscv: rvv-1.0: floating-point move instruction [v6,37/72] target/riscv: rvv-1.0: floating-point scalar move instructions [v6,38/72] target/riscv: rvv-1.0: whole register move instructions [v6,39/72] target/riscv: rvv-1.0: integer extension instructions [v6,40/72] target/riscv: rvv-1.0: single-width averaging add and subtract instructions [v6,41/72] target/riscv: rvv-1.0: single-width bit shift instructions [v6,42/72] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow [v6,43/72] target/riscv: rvv-1.0: narrowing integer right shift instructions [v6,44/72] target/riscv: rvv-1.0: widening integer multiply-add instructions [v6,45/72] target/riscv: rvv-1.0: single-width saturating add and subtract instructions [v6,46/72] target/riscv: rvv-1.0: integer comparison instructions [v6,47/72] target/riscv: rvv-1.0: floating-point compare instructions [v6,48/72] target/riscv: rvv-1.0: mask-register logical instructions [v6,49/72] target/riscv: rvv-1.0: slide instructions [v6,50/72] target/riscv: rvv-1.0: floating-point slide instructions [v6,51/72] target/riscv: rvv-1.0: narrowing fixed-point clip instructions [v6,52/72] target/riscv: rvv-1.0: single-width floating-point reduction [v6,53/72] target/riscv: rvv-1.0: widening floating-point reduction instructions [v6,54/72] target/riscv: rvv-1.0: single-width scaling shift instructions [v6,55/72] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add [v6,56/72] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf [v6,57/72] target/riscv: rvv-1.0: remove integer extract instruction [v6,58/72] target/riscv: rvv-1.0: floating-point min/max instructions [v6,59/72] target/riscv: introduce floating-point rounding mode enum [v6,60/72] target/riscv: rvv-1.0: floating-point/integer type-convert instructions [v6,61/72] target/riscv: rvv-1.0: widening floating-point/integer type-convert [v6,62/72] target/riscv: add "set round to odd" rounding mode helper function [v6,63/72] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert [v6,64/72] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits [v6,65/72] target/riscv: rvv-1.0: implement vstart CSR [v6,66/72] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid [v6,67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs [v6,68/72] target/riscv: gdb: modify gdb csr xml file to align with csr register map [v6,69/72] target/riscv: gdb: support vector registers for rv64 & rv32 [v6,70/72] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction [v6,71/72] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction [v6,72/72] target/riscv: set mstatus.SD bit when writing fp CSRs

[v6,67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs

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