| Message ID | 20221201140811.142123-9-bmeng@tinylab.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC | expand |
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote: > Per chapter 6.5.2 in [1], the number of interupt sources including > interrupt source 0 should be 187. > > [1] PolarFire SoC MSS TRM: > https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf > > Fixes: 56f6e31e7b7e ("hw/riscv: Initial support for Microchip > PolarFire SoC Icicle Kit board") > Signed-off-by: Bin Meng <bmeng@tinylab.org> > --- > > include/hw/riscv/microchip_pfsoc.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> > diff --git a/include/hw/riscv/microchip_pfsoc.h > b/include/hw/riscv/microchip_pfsoc.h > index a757b240e0..9720bac2d5 100644 > --- a/include/hw/riscv/microchip_pfsoc.h > +++ b/include/hw/riscv/microchip_pfsoc.h > @@ -150,7 +150,7 @@ enum { > #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 > #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 > > -#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185 > +#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187 > #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 > #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 > #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
On Fri, Dec 2, 2022 at 12:11 AM Bin Meng <bmeng@tinylab.org> wrote: > > Per chapter 6.5.2 in [1], the number of interupt sources including > interrupt source 0 should be 187. > > [1] PolarFire SoC MSS TRM: > https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf > > Fixes: 56f6e31e7b7e ("hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board") > Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > include/hw/riscv/microchip_pfsoc.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h > index a757b240e0..9720bac2d5 100644 > --- a/include/hw/riscv/microchip_pfsoc.h > +++ b/include/hw/riscv/microchip_pfsoc.h > @@ -150,7 +150,7 @@ enum { > #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 > #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 > > -#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185 > +#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187 > #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 > #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 > #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 > -- > 2.34.1 > >
On Thu, Dec 01, 2022 at 10:08:05PM +0800, Bin Meng wrote: > Per chapter 6.5.2 in [1], the number of interupt sources including > interrupt source 0 should be 187. > > [1] PolarFire SoC MSS TRM: > https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks! > > Fixes: 56f6e31e7b7e ("hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board") > Signed-off-by: Bin Meng <bmeng@tinylab.org> > --- > > include/hw/riscv/microchip_pfsoc.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h > index a757b240e0..9720bac2d5 100644 > --- a/include/hw/riscv/microchip_pfsoc.h > +++ b/include/hw/riscv/microchip_pfsoc.h > @@ -150,7 +150,7 @@ enum { > #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 > #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 > > -#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185 > +#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187 > #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 > #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 > #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 > -- > 2.34.1 > > >
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index a757b240e0..9720bac2d5 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -150,7 +150,7 @@ enum { #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 -#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185 +#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187 #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
Per chapter 6.5.2 in [1], the number of interupt sources including interrupt source 0 should be 187. [1] PolarFire SoC MSS TRM: https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf Fixes: 56f6e31e7b7e ("hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board") Signed-off-by: Bin Meng <bmeng@tinylab.org> --- include/hw/riscv/microchip_pfsoc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)