Show patches with: Submitter = Ville Syrjälä       |    State = Action Required       |    Archived = No       |   3748 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,1/9] drm/i915: Implement WaEnableHDMI8bpcBefore12bpc:snb, ivb - - - 0 0 0 2015-05-05 Ville Syrjälä New
[v2,2/9] drm/i915: Send GCP infoframes for deep color HDMI sinks - - - 0 0 0 2015-05-05 Ville Syrjälä New
[v2,3/9] drm/i915: Enable default_phase in GCP when possible - - - 0 0 0 2015-05-05 Ville Syrjälä New
[v2,4/9] drm/i915: Fix HDMI 12bpc TRANSCONF bpc value - - - 0 0 0 2015-05-05 Ville Syrjälä New
[v2,5/9] drm/i915: Fix 12bpc HDMI enable for IBX - - - 0 0 0 2015-05-05 Ville Syrjälä New
[v2,6/9] drm/i915: Disable all infoframes when turning off the HDMI port - - - 0 0 0 2015-05-05 Ville Syrjälä New
[7/9] drm/i915: Check infoframe state more diligently. - - - 0 0 0 2015-05-05 Ville Syrjälä New
[8/9] drm/i915: Fix hdmi clock readout with pixel repeat - - - 0 0 0 2015-05-05 Ville Syrjälä New
[9/9] drm/i915: Double the port clock when using double clocked modes with 12bpc - - - 0 0 0 2015-05-05 Ville Syrjälä New
[01/12] drm/i915: Remove a bogus 12bpc "toggle" from intel_disable_hdmi() - - - 0 0 0 2015-05-05 Ville Syrjälä New
[02/12] drm/i915: Remove the double register write from intel_disable_hdmi() - - - 0 0 0 2015-05-05 Ville Syrjälä New
[03/12] drm/i915: Clarfify the DP code platform checks - - - 0 0 0 2015-05-05 Ville Syrjälä New
[04/12] drm/i915: Clean up the CPT DP .get_hw_state() port readout - - - 0 0 0 2015-05-05 Ville Syrjälä New
[05/12] drm/i915: Fix DP enhanced framing for CPT - - - 0 0 0 2015-05-05 Ville Syrjälä New
[06/12] drm/i915: Use POSTING_READ() in intel_sdvo_write_sdvox() - - - 0 0 0 2015-05-05 Ville Syrjälä New
[07/12] drm/i915: Write the SDVO reg twice on IBX - - - 0 0 0 2015-05-05 Ville Syrjälä New
[08/12] drm/i915: Fix the IBX transcoder B workarounds - - - 0 0 0 2015-05-05 Ville Syrjälä New
[09/12] drm/i915: Disable HDMI port after the pipe on PCH platforms - - - 0 0 0 2015-05-05 Ville Syrjälä New
[10/12] drm/i915: Disable SDVO port after the pipe on PCH platforms - - - 0 0 0 2015-05-05 Ville Syrjälä New
[11/12] drm/i915: Disable CRT port after pipe on PCH platforms - - - 0 0 0 2015-05-05 Ville Syrjälä New
[12/12] drm/i915: Disable FDI RX/TX before the ports - - - 0 0 0 2015-05-05 Ville Syrjälä New
drm/i915: Add missing POSTING_READ()s to BXT dbuf enable sequence - - - 0 0 0 2015-05-06 Ville Syrjälä New
[i-g-t] tests/kms_3d: Reduce the number of expected stereo 3D modes - - - 0 0 0 2015-05-08 Ville Syrjälä New
[1/2] drm/i915: Remove excess inline keywords - - - 0 0 0 2015-05-11 Ville Syrjälä New
[2/2] drm/i915: Use HOTPLUG_INT_STATUS_G4X on VLV/CHV - - - 0 0 0 2015-05-11 Ville Syrjälä New
[1/3] drm/i915: Use ilk_init_lp_watermarks() on BDW - - - 0 0 0 2015-05-19 Ville Syrjälä New
[2/3] drm/i915: Move WaProgramL3SqcReg1Default:bdw to init_clock_gating() - - - 0 0 0 2015-05-19 Ville Syrjälä New
[3/3] drm/i915: Enable GTT caching on gen8 - - - 0 0 0 2015-05-19 Ville Syrjälä New
[1/3] drm/i915: Use the default 600ns LDO programming sequence delay - - - 0 0 0 2015-05-26 Ville Syrjälä New
[2/3] drm/i915: Throw out WIP CHV power well definitions - - - 0 0 0 2015-05-26 Ville Syrjälä New
[3/3] drm/i915: Bump CHV PFI credits to 63 when cdclk>=czclk - - - 0 0 0 2015-05-26 Ville Syrjälä New
drm/i915: Kill intel_flush_primary_plane() - - - 0 0 0 2015-05-26 Ville Syrjälä New
[1/2] drm/i915: s/dpio_lock/sb_lock/ - - - 0 0 0 2015-05-26 Ville Syrjälä New
[2/2] drm/i915: Adjust sideband locking a bit for CHV/VLV - - - 0 0 0 2015-05-26 Ville Syrjälä New
drm/i915: Don't skip request retirement if the active list is empty - - - 0 0 0 2015-05-28 Ville Syrjälä New
[1/3] drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code - - - 0 0 0 2015-06-02 Ville Syrjälä New
[2/3] drm/i915: Set INSTPM_FORCE_ORDERING via LRI on gen8, drop it on gen9+ - - - 0 0 0 2015-06-02 Ville Syrjälä New
[3/3] drm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs on gen8 - - - 0 0 0 2015-06-02 Ville Syrjälä New
drm/i915: Make sure our labels start at column 0 - - - 0 0 0 2015-06-04 Ville Syrjälä New
[1/3] drm/i915: Actually respect DSPSURF alignment restrictions - - - 0 0 0 2015-06-11 Ville Syrjälä New
[2/3] drm/i915: Align DSPSURF to 128k on VLV/CHV - - - 0 0 0 2015-06-11 Ville Syrjälä New
[3/3] drm/i915: Drop the 64k linear scanout alignment on gen2/3 - - - 0 0 0 2015-06-11 Ville Syrjälä New
drm/i915: Ignore -EIO from __i915_wait_request() during mmio flip - - - 0 0 0 2015-06-11 Ville Syrjälä New
[v2] drm/i915: Ignore -EIO from __i915_wait_request() during flips - - - 0 0 0 2015-06-11 Ville Syrjälä New
[1/2] drm/i915: Fix HDMI 12bpc and pixel repeat clock readout for DDI platforms - - - 0 0 0 2015-06-17 Ville Syrjälä New
[2/2] Revert "drm/i915: Disable 12bpc hdmi for now" - - - 0 0 0 2015-06-17 Ville Syrjälä New
drm/i915: Factor out p2 divider selection for pre-ilk platforms - - - 0 0 0 2015-06-18 Ville Syrjälä New
[1/3] drm/i915: Store frontbuffer_bits in the plane - - - 0 0 0 2015-06-24 Ville Syrjälä New
[2/3] drm/i915: Add debug messages for pipe enable/disable - - - 0 0 0 2015-06-24 Ville Syrjälä New
[3/3] drm/i915: Don't set cursor rotate bits when cursor is disabled - - - 0 0 0 2015-06-24 Ville Syrjälä New
[01/10] drm/i915: POSTING_READ() in intel_set_memory_cxsr() - - - 0 0 0 2015-06-24 Ville Syrjälä New
[02/10] drm/i915: Split atomic wm update to pre and post variants - - - 0 0 0 2015-06-24 Ville Syrjälä New
[03/10] drm/i915: Read wm values from hardware at init on CHV - - - 0 0 0 2015-06-24 Ville Syrjälä New
[04/10] drm/i915: CHV DDR DVFS support and another watermark rewrite - - - 0 0 0 2015-06-24 Ville Syrjälä New
[05/10] drm/i915: Compute display FIFO split dynamically for CHV - - - 0 0 0 2015-06-24 Ville Syrjälä New
[06/10] drm/i915: Use the memory latency based WM computation on VLV too - - - 0 0 0 2015-06-24 Ville Syrjälä New
[07/10] drm/i915: Try to make sure cxsr is disabled around plane enable/disable - - - 0 0 0 2015-06-24 Ville Syrjälä New
[08/10] drm/i915: Don't do PM5/DDR DVFS with multiple pipes - - - 0 0 0 2015-06-24 Ville Syrjälä New
[09/10] drm/i915: Add debugfs knobs for VLVCHV memory latency values - - - 0 0 0 2015-06-24 Ville Syrjälä New
[10/10] drm/i915: Zero unused WM1 watermarks on VLV/CHV - - - 0 0 0 2015-06-24 Ville Syrjälä New
[1/9] drm/i915: Keep GMCH DPLL VGA mode always disabled - - - 0 0 0 2015-06-29 Ville Syrjälä New
[2/9] drm/i915: Apply OCD to VLV/CHV DPLL defines - - - 0 0 0 2015-06-29 Ville Syrjälä New
[3/9] drm/i915: Simplify CHV pipe A power well code - - - 0 0 0 2015-06-29 Ville Syrjälä New
[4/9] drm/i915: Refactor VLV display power well init/deinit - - - 0 0 0 2015-06-29 Ville Syrjälä New
[5/9] drm/i915: Clear out DPLL state from pipe config in DSI get config - - - 0 0 0 2015-06-29 Ville Syrjälä New
[6/9] drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable - - - 0 0 0 2015-06-29 Ville Syrjälä New
[7/9] drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar - - - 0 0 0 2015-06-29 Ville Syrjälä New
[8/9] drm/i915: Implement WaPixelRepeatModeFixForC0:chv - - - 0 0 0 2015-06-29 Ville Syrjälä New
[9/9] drm/i915: Disable DSI PLL before reconfiguring it - - - 0 0 0 2015-06-29 Ville Syrjälä New
Revert "drm/i915: Allocate context objects from stolen" - - - 0 0 0 2015-06-29 Ville Syrjälä New
[1/4] drm/i915: Fix HDMI 12bpc and pixel repeat clock readout for DDI platforms - - - 0 0 0 2015-06-30 Ville Syrjälä New
[2/4] drm/i915: Bump HDMI min port clock to 25 MHz - - - 0 0 0 2015-06-30 Ville Syrjälä New
[3/4] drm/i915: Account for CHV/BXT DPLL clock limitations - - - 0 0 0 2015-06-30 Ville Syrjälä New
[4/4] Revert "drm/i915: Disable 12bpc hdmi for now" - - - 0 0 0 2015-06-30 Ville Syrjälä New
[v2,3/4] drm/i915: Account for CHV/BXT DPLL clock limitations - - - 0 0 0 2015-06-30 Ville Syrjälä New
[v2,07/10] drm/i915: Try to make sure cxsr is disabled around plane enable/disable - - - 0 0 0 2015-07-01 Ville Syrjälä New
drm/i915: Disable LVDS port after the pipe on PCH - - - 0 0 0 2015-07-02 Ville Syrjälä New
drm/i915: Drop a spurious intel_pre_plane_update() call - - - 0 0 0 2015-07-03 Ville Syrjälä New
drm/i915: Adjust BXT HDMI port clock limits - - - 0 0 0 2015-07-06 Ville Syrjälä New
[1/7] drm/i915: Clean up DP/HDMI limited color range handling - - - 0 0 0 2015-07-06 Ville Syrjälä New
[2/7] drm/i915: Don't use link_bw for PLL setup - - - 0 0 0 2015-07-06 Ville Syrjälä New
[3/7] drm/i915: Don't pass clock to DDI PLL select functions - - - 0 0 0 2015-07-06 Ville Syrjälä New
[4/7] drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP .get_config() - - - 0 0 0 2015-07-06 Ville Syrjälä New
[5/7] drm/i915: Move intel_dp->lane_count into pipe_config - - - 0 0 0 2015-07-06 Ville Syrjälä New
[6/7] drm/i915: Don't use link_bw to select between TP1 and TP3 - - - 0 0 0 2015-07-06 Ville Syrjälä New
[7/7] drm/i915: Kill intel_dp->{link_bw, rate_select} - - - 0 0 0 2015-07-06 Ville Syrjälä New
drm/i915: Improve DP downstream HPD handling - - - 0 0 0 2015-07-06 Ville Syrjälä New
[v2,5/7] drm/i915: Move intel_dp->lane_count into pipe_config - - - 0 0 0 2015-07-06 Ville Syrjälä New
[01/15] drm/i915: Always program m2 fractional value on CHV - - - 0 0 0 2015-07-08 Ville Syrjälä New
[02/15] drm/i915: Always program unique transition scale for CHV - - - 0 0 0 2015-07-08 Ville Syrjälä New
[03/15] drm/i915: Add encoder->post_pll_disable() hooks and move CHV clock buffer disables there - - - 0 0 0 2015-07-08 Ville Syrjälä New
[04/15] drm/i915: Move DPIO port init earlier - - - 0 0 0 2015-07-08 Ville Syrjälä New
[05/15] drm/i915: Add locking around chv_phy_control_init() - - - 0 0 0 2015-07-08 Ville Syrjälä New
[06/15] drm/i915: Move VLV/CHV prepare_pll later - - - 0 0 0 2015-07-08 Ville Syrjälä New
[07/15] drm/i915: Add vlv_dport_to_phy() - - - 0 0 0 2015-07-08 Ville Syrjälä New
[08/15] drm/i915: Implement PHY lane power gating for CHV - - - 0 0 0 2015-07-08 Ville Syrjälä New
[09/15] drm/i915: Trick CL2 into life on CHV when using pipe B with port B - - - 0 0 0 2015-07-08 Ville Syrjälä New
[10/15] drm/i915: Force common lane on for the PPS kick on CHV - - - 0 0 0 2015-07-08 Ville Syrjälä New
[11/15] drm/i915: Enable DPIO SUS clock gating on CHV - - - 0 0 0 2015-07-08 Ville Syrjälä New
[12/15] drm/i915: Force CL2 off in CHV x1 PHY - - - 0 0 0 2015-07-08 Ville Syrjälä New
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