@@ -241,3 +241,14 @@ config DRM_I915_PLATFORM_INTEL_CANNONLAKE
help
Include support for Intel Cannonlake platforms.
+config DRM_I915_GEN11
+ bool
+
+config DRM_I915_PLATFORM_INTEL_ICELAKE
+ bool "Intel Icelake platform support"
+ default y
+ depends on DRM_I915
+ select DRM_I915_GEN11
+ help
+ Include support for Intel Icelake platforms.
+
@@ -2612,7 +2612,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_GEMINILAKE(dev_priv) IS_OPT_PLATFORM(dev_priv, INTEL_GEMINILAKE)
#define IS_COFFEELAKE(dev_priv) IS_OPT_PLATFORM(dev_priv, INTEL_COFFEELAKE)
#define IS_CANNONLAKE(dev_priv) IS_OPT_PLATFORM(dev_priv, INTEL_CANNONLAKE)
-#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
+#define IS_ICELAKE(dev_priv) IS_OPT_PLATFORM(dev_priv, INTEL_ICELAKE)
#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
@@ -2750,7 +2750,9 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_GEN10(dev_priv) \
(IS_ENABLED(CONFIG_DRM_I915_GEN10) && \
((dev_priv)->info.gen_mask & BIT(9)))
-#define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
+#define IS_GEN11(dev_priv) \
+ (IS_ENABLED(CONFIG_DRM_I915_GEN11) && \
+ ((dev_priv)->info.gen_mask & BIT(10)))
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
@@ -645,12 +645,14 @@ static const struct intel_device_info intel_cannonlake_info = {
.ddb_size = 2048, \
.has_csr = 0
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_ICELAKE
static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
.platform = INTEL_ICELAKE,
.is_alpha_support = 1,
.has_resource_streamer = 0,
};
+#endif
/*
* Make sure any device matches here are from most specific to most