diff mbox series

[16/42] drm/i915/xe2lpd: Move D2D enable/disable

Message ID 20230823170740.1180212-17-lucas.demarchi@intel.com (mailing list archive)
State New, archived
Headers show
Series Enable Lunar Lake display | expand

Commit Message

Lucas De Marchi Aug. 23, 2023, 5:07 p.m. UTC 
Bits to enable/disable and check state for D2D moved from
XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL. Make the functions
mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic to work with
multiple reg location and bitfield layout.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 38 +++++++++++++++++-------
 drivers/gpu/drm/i915/i915_reg.h          |  2 ++
 2 files changed, 30 insertions(+), 10 deletions(-)

Comments

Matt Roper Aug. 23, 2023, 7:01 p.m. UTC | #1 
On Wed, Aug 23, 2023 at 10:07:14AM -0700, Lucas De Marchi wrote:
> Bits to enable/disable and check state for D2D moved from
> XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL. Make the functions

As of Xe2, DDI_BUF_CTL is now renamed to "DDI_CTL_DE" in the spec, so
you might want to toss a mention of the new register name in the commit
message here to make it easier to lookup in the spec.  E.g.,
"... (now named DDI_CTL_DE in the spec) ..."  Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic to work with
> multiple reg location and bitfield layout.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 38 +++++++++++++++++-------
>  drivers/gpu/drm/i915/i915_reg.h          |  2 ++
>  2 files changed, 30 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 61722556bb47..a9440c0ecf61 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2356,13 +2356,22 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
> +	i915_reg_t reg;
> +	u32 set_bits, wait_bits;
>  
> -	intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0,
> -		     XELPDP_PORT_BUF_D2D_LINK_ENABLE);
> +	if (DISPLAY_VER(dev_priv) >= 20) {
> +		reg = DDI_BUF_CTL(port);
> +		set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> +		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
> +	} else {
> +		reg = XELPDP_PORT_BUF_CTL1(port);
> +		set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
> +		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
> +	}
>  
> -	if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
> -			 XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) {
> -		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for PORT_BUF_CTL %c\n",
> +	intel_de_rmw(dev_priv, reg, 0, set_bits);
> +	if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) {
> +		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
>  			port_name(port));
>  	}
>  }
> @@ -2809,13 +2818,22 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
> +	i915_reg_t reg;
> +	u32 clr_bits, wait_bits;
>  
> -	intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
> -		     XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0);
> +	if (DISPLAY_VER(dev_priv) >= 20) {
> +		reg = DDI_BUF_CTL(port);
> +		clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> +		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
> +	} else {
> +		reg = XELPDP_PORT_BUF_CTL1(port);
> +		clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
> +		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
> +	}
>  
> -	if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
> -			  XELPDP_PORT_BUF_D2D_LINK_STATE), 100))
> -		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for PORT_BUF_CTL %c\n",
> +	intel_de_rmw(dev_priv, reg, clr_bits, 0);
> +	if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100))
> +		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
>  			port_name(port));
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dcf64e32cd54..84c5a76065a0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5723,6 +5723,8 @@ enum skl_power_gate {
>  /* Known as DDI_CTL_DE in MTL+ */
>  #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
>  #define  DDI_BUF_CTL_ENABLE			(1 << 31)
> +#define  XE2LPD_DDI_BUF_D2D_LINK_ENABLE		REG_BIT(29)
> +#define  XE2LPD_DDI_BUF_D2D_LINK_STATE		REG_BIT(28)
>  #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
>  #define  DDI_BUF_EMP_MASK			(0xf << 24)
>  #define  DDI_BUF_PHY_LINK_RATE(r)		((r) << 20)
> -- 
> 2.40.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 61722556bb47..a9440c0ecf61 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2356,13 +2356,22 @@  mtl_ddi_enable_d2d(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+	i915_reg_t reg;
+	u32 set_bits, wait_bits;
 
-	intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0,
-		     XELPDP_PORT_BUF_D2D_LINK_ENABLE);
+	if (DISPLAY_VER(dev_priv) >= 20) {
+		reg = DDI_BUF_CTL(port);
+		set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
+	} else {
+		reg = XELPDP_PORT_BUF_CTL1(port);
+		set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
+		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
+	}
 
-	if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
-			 XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) {
-		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for PORT_BUF_CTL %c\n",
+	intel_de_rmw(dev_priv, reg, 0, set_bits);
+	if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) {
+		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
 			port_name(port));
 	}
 }
@@ -2809,13 +2818,22 @@  mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+	i915_reg_t reg;
+	u32 clr_bits, wait_bits;
 
-	intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
-		     XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0);
+	if (DISPLAY_VER(dev_priv) >= 20) {
+		reg = DDI_BUF_CTL(port);
+		clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+		wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
+	} else {
+		reg = XELPDP_PORT_BUF_CTL1(port);
+		clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
+		wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
+	}
 
-	if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
-			  XELPDP_PORT_BUF_D2D_LINK_STATE), 100))
-		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for PORT_BUF_CTL %c\n",
+	intel_de_rmw(dev_priv, reg, clr_bits, 0);
+	if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100))
+		drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
 			port_name(port));
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dcf64e32cd54..84c5a76065a0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5723,6 +5723,8 @@  enum skl_power_gate {
 /* Known as DDI_CTL_DE in MTL+ */
 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
 #define  DDI_BUF_CTL_ENABLE			(1 << 31)
+#define  XE2LPD_DDI_BUF_D2D_LINK_ENABLE		REG_BIT(29)
+#define  XE2LPD_DDI_BUF_D2D_LINK_STATE		REG_BIT(28)
 #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
 #define  DDI_BUF_EMP_MASK			(0xf << 24)
 #define  DDI_BUF_PHY_LINK_RATE(r)		((r) << 20)