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[v2,16/25] drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR

Message ID 20240403112253.1432390-17-balasubramani.vivekanandan@intel.com (mailing list archive)
State New
Headers show
Series Enable dislay support for Battlemage | expand

Commit Message

Balasubramani Vivekanandan April 3, 2024, 11:22 a.m. UTC
Defined a new DRAM type to be used in the following patches.
The following patch first makes use of this new type in the i915
display. So without this define, build would fail when the shared
display code is built for Xe.

Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
 drivers/gpu/drm/xe/xe_device_types.h | 1 +
 1 file changed, 1 insertion(+)

Comments

Jani Nikula April 3, 2024, 11:53 a.m. UTC | #1
On Wed, 03 Apr 2024, Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> wrote:
> Defined a new DRAM type to be used in the following patches.
> The following patch first makes use of this new type in the i915
> display. So without this define, build would fail when the shared
> display code is built for Xe.

Just make it part of that patch I think.

>
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_device_types.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 1df3dcc17d75..e7aa2dd3df8d 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -480,6 +480,7 @@ struct xe_device {
>  			INTEL_DRAM_LPDDR4,
>  			INTEL_DRAM_DDR5,
>  			INTEL_DRAM_LPDDR5,
> +			INTEL_DRAM_GDDR,
>  		} type;
>  		u8 num_qgv_points;
>  		u8 num_psf_gv_points;
diff mbox series

Patch

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 1df3dcc17d75..e7aa2dd3df8d 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -480,6 +480,7 @@  struct xe_device {
 			INTEL_DRAM_LPDDR4,
 			INTEL_DRAM_DDR5,
 			INTEL_DRAM_LPDDR5,
+			INTEL_DRAM_GDDR,
 		} type;
 		u8 num_qgv_points;
 		u8 num_psf_gv_points;