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[v2,08/25] drm/i915/bmg: Extend DG2 tc check to future

Message ID 20240403112253.1432390-9-balasubramani.vivekanandan@intel.com (mailing list archive)
State New
Headers show
Series Enable dislay support for Battlemage | expand

Commit Message

Balasubramani Vivekanandan April 3, 2024, 11:22 a.m. UTC 
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>

Discrete cards use the Port numbers TC1-4 for the offsets. The regular
flow for type-c subsystem port initialization can be skipped. This check
is present in DG2. Extend this to future discrete products.

Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

Comments

Matt Roper April 3, 2024, 7:15 p.m. UTC | #1 
On Wed, Apr 03, 2024 at 04:52:36PM +0530, Balasubramani Vivekanandan wrote:
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> 
> Discrete cards use the Port numbers TC1-4 for the offsets. The regular
> flow for type-c subsystem port initialization can be skipped. This check
> is present in DG2. Extend this to future discrete products.
> 
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 7 +++----
>  1 file changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 614e60420a29..aed25890b6f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1861,11 +1861,10 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
>  bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>  {
>  	/*
> -	 * DG2's "TC1", although TC-capable output, doesn't share the same flow
> -	 * as other platforms on the display engine side and rather rely on the
> -	 * SNPS PHY, that is programmed separately
> +	 * Discrete GPU phy's are not attached to FIA's to support TC
> +	 * subsystem Legacy or non-legacy, and only support native DP/HDMI
>  	 */
> -	if (IS_DG2(dev_priv))
> +	if (IS_DGFX(dev_priv))
>  		return false;
>  
>  	if (DISPLAY_VER(dev_priv) >= 13)
> -- 
> 2.25.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 614e60420a29..aed25890b6f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1861,11 +1861,10 @@  bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 {
 	/*
-	 * DG2's "TC1", although TC-capable output, doesn't share the same flow
-	 * as other platforms on the display engine side and rather rely on the
-	 * SNPS PHY, that is programmed separately
+	 * Discrete GPU phy's are not attached to FIA's to support TC
+	 * subsystem Legacy or non-legacy, and only support native DP/HDMI
 	 */
-	if (IS_DG2(dev_priv))
+	if (IS_DGFX(dev_priv))
 		return false;
 
 	if (DISPLAY_VER(dev_priv) >= 13)