| Message ID | 20240403112253.1432390-21-balasubramani.vivekanandan@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Enable dislay support for Battlemage | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of > Balasubramani Vivekanandan > Sent: Wednesday, April 3, 2024 4:53 PM > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org > Cc: Roper, Matthew D <matthew.d.roper@intel.com>; De Marchi, Lucas > <lucas.demarchi@intel.com>; Vivekanandan, Balasubramani > <balasubramani.vivekanandan@intel.com> > Subject: [PATCH v2 20/25] drm/i915/bmg: BMG should re-use MTL's south > display logic > > From: Matt Roper <matthew.d.roper@intel.com> > > Battlemage's south display is the same as Meteor Lake's, including the need to ^^^ Hi Bala, We might want to rephrase this description a bit to fit in sentence. > invert the HPD pins, which Lunar Lake does not need. > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Balasubramani Vivekanandan > <balasubramani.vivekanandan@intel.com> > --- With this change LGTM. Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Dnyaneshwar Bhadane > drivers/gpu/drm/i915/soc/intel_pch.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c > b/drivers/gpu/drm/i915/soc/intel_pch.c > index 3cad6dac06b0..542eea50093c 100644 > --- a/drivers/gpu/drm/i915/soc/intel_pch.c > +++ b/drivers/gpu/drm/i915/soc/intel_pch.c > @@ -218,10 +218,10 @@ void intel_detect_pch(struct drm_i915_private > *dev_priv) > if (DISPLAY_VER(dev_priv) >= 20) { > dev_priv->pch_type = PCH_LNL; > return; > - } else if (IS_METEORLAKE(dev_priv)) { > + } else if (IS_BATTLEMAGE(dev_priv) || IS_METEORLAKE(dev_priv)) { > /* > * Both north display and south display are on the SoC die. > - * The real PCH is uninvolved in display. > + * The real PCH (if it even exists) is uninvolved in display. > */ > dev_priv->pch_type = PCH_MTL; > return; > -- > 2.25.1
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c index 3cad6dac06b0..542eea50093c 100644 --- a/drivers/gpu/drm/i915/soc/intel_pch.c +++ b/drivers/gpu/drm/i915/soc/intel_pch.c @@ -218,10 +218,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) if (DISPLAY_VER(dev_priv) >= 20) { dev_priv->pch_type = PCH_LNL; return; - } else if (IS_METEORLAKE(dev_priv)) { + } else if (IS_BATTLEMAGE(dev_priv) || IS_METEORLAKE(dev_priv)) { /* * Both north display and south display are on the SoC die. - * The real PCH is uninvolved in display. + * The real PCH (if it even exists) is uninvolved in display. */ dev_priv->pch_type = PCH_MTL; return;