diff mbox series

[08/16] arm64: dts: qcom: sm8550-aim300: add WCD9385 audio-codec

Message ID 20231117101817.4401-9-quic_tengfan@quicinc.com (mailing list archive)
State Changes Requested
Headers show
Series arm64: qcom: add sm8550-aim300 board support | expand

Commit Message

Tengfei Fan Nov. 17, 2023, 10:18 a.m. UTC
Add Qualcomm Aqstic WCD9385 audio codec on two Soundwire interfaces: RX
and TX.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 57 ++++++++++++++++++++++
 1 file changed, 57 insertions(+)

Comments

Krzysztof Kozlowski Nov. 17, 2023, 10:31 a.m. UTC | #1
On 17/11/2023 11:18, Tengfei Fan wrote:
> Add Qualcomm Aqstic WCD9385 audio codec on two Soundwire interfaces: RX
> and TX.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>

You just added this board. Does it mean you added incomplete and wrong DTS?

Best regards,
Krzysztof
Tengfei Fan Nov. 21, 2023, 12:54 a.m. UTC | #2
在 11/17/2023 6:31 PM, Krzysztof Kozlowski 写道:
> On 17/11/2023 11:18, Tengfei Fan wrote:
>> Add Qualcomm Aqstic WCD9385 audio codec on two Soundwire interfaces: RX
>> and TX.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> 
> You just added this board. Does it mean you added incomplete and wrong DTS?
> 
> Best regards,
> Krzysztof
> 

Hi Krzysztof,
In next version patch series, I will do a board patch which contain all 
the functions which were splited in current patch series.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
index 3aca0a433a00..6a9b384c4e08 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
@@ -24,6 +24,33 @@ 
 		serial0 = &uart7;
 	};
 
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9385-codec";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&wcd_default>;
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000
+							  500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		reset-gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+
+		#sound-dai-cells = <1>;
+
+		vdd-buck-supply = <&vreg_l15b_1p8>;
+		vdd-rxtx-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l15b_1p8>;
+		vdd-mic-bias-supply = <&vreg_bob1>;
+	};
+
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
@@ -456,8 +483,38 @@ 
 	clock-frequency = <32000>;
 };
 
+&swr1 {
+	status = "okay";
+
+	/* WCD9385 RX */
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	/* WCD9385 TX */
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <1 1 2 3>;
+	};
+};
+
 &tlmm {
 	gpio-reserved-ranges = <32 8>;
+
+	wcd_default: wcd-reset-n-active-state {
+		pins = "gpio108";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
 };
 
 &uart7 {