[01/12] riscv: Add SOPHGO SOC family Kconfig support

Message ID	20230915071005.117575-1-wangchen20@iscas.ac.cn (mailing list archive)
State	Superseded
Delegated to:	Conor Dooley
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> From: Wang Chen <unicornxw@gmail.com> To: linux-riscv@lists.infradead.org, conor@kernel.org, aou@eecs.berkeley.edu, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jszhang@kernel.org, guoren@kernel.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, Wang Chen <wangchen20@iscas.ac.cn> Subject: [PATCH 01/12] riscv: Add SOPHGO SOC family Kconfig support Date: Fri, 15 Sep 2023 15:10:05 +0800 Message-Id: <20230915071005.117575-1-wangchen20@iscas.ac.cn> MIME-Version: 1.0 Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	Add Milk-V Pioneer RISC-V board support \| expand [00/12] Add Milk-V Pioneer RISC-V board support [01/12] riscv: Add SOPHGO SOC family Kconfig support [02/12] dt-bindings: vendor-prefixes: add milkv/sophgo [03/12] dt-bindings: riscv: add sophgo sg2042 bindings [04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles [05/12] dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC [06/12] dt-bindings: timer: Add Sophgo sg2042 clint [07/12] riscv: dts: add initial SOPHGO SG2042 SoC device tree [08/12] riscv: dts: sophgo: add Milk-V Pioneer board device tree [09/12] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts [10/12] serial: 8250_dw: Add Sophgo SG2042 support [11/12] riscv: dts: sophgo: Add sophgo,sg2024-uart compatibles [12/12] riscv: defconfig: enable SOPHGO SoC

Message ID

20230915071005.117575-1-wangchen20@iscas.ac.cn (mailing list archive)

State

Superseded

Delegated to:

Conor Dooley

Headers

From: Wang Chen <unicornxw@gmail.com>
To: linux-riscv@lists.infradead.org,
	conor@kernel.org,
	aou@eecs.berkeley.edu,
	krzysztof.kozlowski+dt@linaro.org,
	palmer@dabbelt.com,
	paul.walmsley@sifive.com,
	robh+dt@kernel.org
Cc: devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	jszhang@kernel.org,
	guoren@kernel.org,
	chao.wei@sophgo.com,
	xiaoguang.xing@sophgo.com,
	Wang Chen <wangchen20@iscas.ac.cn>
Subject: [PATCH 01/12] riscv: Add SOPHGO SOC family Kconfig support
Date: Fri, 15 Sep 2023 15:10:05 +0800
Message-Id: <20230915071005.117575-1-wangchen20@iscas.ac.cn>
MIME-Version: 1.0
Precedence: list
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Errors-To: 
 linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org

Series

Add Milk-V Pioneer RISC-V board support | expand

Commit Message

Chen Wang Sept. 15, 2023, 7:10 a.m. UTC

From: "xiaoguang.xing" <xiaoguang.xing@sophgo.com>

The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V
cores.

Signed-off-by: xiaoguang.xing <xiaoguang.xing@sophgo.com>
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
---
 arch/riscv/Kconfig.socs | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Krzysztof Kozlowski Sept. 15, 2023, 7:20 a.m. UTC | #1

On 15/09/2023 09:10, Wang Chen wrote:
> From: "xiaoguang.xing" <xiaoguang.xing@sophgo.com>
> 
> The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V
> cores.
> 
> Signed-off-by: xiaoguang.xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>

Your patch threading is completely broken/missing, so this makes review
unnecessary difficult. Fix your process (e.g. use b4).

Best regards,
Krzysztof

Conor Dooley Sept. 15, 2023, 7:21 a.m. UTC | #2

Yo,

On Fri, Sep 15, 2023 at 03:10:05PM +0800, Wang Chen wrote:
> From: "xiaoguang.xing" <xiaoguang.xing@sophgo.com>

This needs to be a name, not the contents of their email address.
Probably just needs the . swapped for a space?

> The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V
> cores.
> 
> Signed-off-by: xiaoguang.xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
> ---
>  arch/riscv/Kconfig.socs | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 6833d01e2e70..fc7b5e6c7def 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -110,4 +110,14 @@ config SOC_CANAAN_K210_DTB_SOURCE
>  
>  endif # ARCH_CANAAN
>  
> +config ARCH_SOPHGO
> +	bool "Sophgo SoCs"
> +	select SIFIVE_PLIC

This should not be needed, this should be selected at the arch level.

> +	help
> +	  This enables support for Sophgo SoC platform hardware.
> +	  SOPHGO is committed to become a provider of universal
> +	  computing power, focusing on the development and
> +	  promotion of computing power products such as AI and
> +	  RISC-V CPU.

This is not a place for marketing blurbs, please take a look at the
other entries.
Also, this should not be placed at the end of the list, it should be
before ARCH_SUNXI.

Thanks,
Conor.

> +
>  endmenu # "SoC selection"
> -- 
> 2.25.1
>

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 6833d01e2e70..fc7b5e6c7def 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -110,4 +110,14 @@  config SOC_CANAAN_K210_DTB_SOURCE
 
 endif # ARCH_CANAAN
 
+config ARCH_SOPHGO
+	bool "Sophgo SoCs"
+	select SIFIVE_PLIC
+	help
+	  This enables support for Sophgo SoC platform hardware.
+	  SOPHGO is committed to become a provider of universal
+	  computing power, focusing on the development and
+	  promotion of computing power products such as AI and
+	  RISC-V CPU.
+
 endmenu # "SoC selection"

[01/12] riscv: Add SOPHGO SOC family Kconfig support

Commit Message

Comments

Patch