| Message ID | 20230915072415.118100-1-wangchen20@iscas.ac.cn (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | Add Milk-V Pioneer RISC-V board support | expand |
On 15/09/2023 09:24, Wang Chen wrote: > From: Inochi Amaoto <inochiama@outlook.com> > > The timer and ipi(mswi) of sg2042 are on different addresses. With the > same compatible string, this will cause a mismatch when is processed by > SBI. No, same devices (obviously on different addresses) with same programming interface have *the same compatible*. > > Add two new compatible string formatted like `C9xx-clint-xxx` to identify > the timer and ipi device separately, and do not allow c900-clint as the > fallback to avoid conflict. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > --- > .../bindings/timer/sifive,clint.yaml | 26 +++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > index a0185e15a42f..2a86b80c3f1e 100644 > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -39,6 +39,14 @@ properties: > - allwinner,sun20i-d1-clint > - thead,th1520-clint > - const: thead,c900-clint > + - items: > + - enum: > + - sophgo,sg2042-clint-mtimer > + - const: thead,c900-clint-mtimer > + - items: > + - enum: > + - sophgo,sg2042-clint-mswi > + - const: thead,c900-clint-mswi > - items: > - const: sifive,clint0 > - const: riscv,clint0 > @@ -74,4 +82,22 @@ examples: > <&cpu4intc 3>, <&cpu4intc 7>; > reg = <0x2000000 0x10000>; > }; > + - | > + clint-mtimer@ac010000 { > + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; > + interrupts-extended = <&cpu1intc 7>, > + <&cpu2intc 7>, > + <&cpu3intc 7>, > + <&cpu4intc 7>; > + reg = <0xac010000 0x00007ff8>; Drop example, not needed. > + }; > + - | > + clint-mswi@94000000 { > + compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi"; > + interrupts-extended = <&cpu1intc 3>, > + <&cpu2intc 3>, > + <&cpu3intc 3>, > + <&cpu4intc 3>; > + reg = <0x94000000 0x00004000>; Drop example, not needed. > + }; > ... Best regards, Krzysztof
On Fri, Sep 15, 2023 at 03:24:15PM +0800, Wang Chen wrote: > From: Inochi Amaoto <inochiama@outlook.com> > > The timer and ipi(mswi) of sg2042 are on different addresses. With the > same compatible string, this will cause a mismatch when is processed by > SBI. > > Add two new compatible string formatted like `C9xx-clint-xxx` to identify > the timer and ipi device separately, and do not allow c900-clint as the > fallback to avoid conflict. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Missing your S-o-b as any patch you send should have yours (last). > --- > .../bindings/timer/sifive,clint.yaml | 26 +++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > index a0185e15a42f..2a86b80c3f1e 100644 > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -39,6 +39,14 @@ properties: > - allwinner,sun20i-d1-clint > - thead,th1520-clint > - const: thead,c900-clint > + - items: > + - enum: > + - sophgo,sg2042-clint-mtimer > + - const: thead,c900-clint-mtimer > + - items: > + - enum: > + - sophgo,sg2042-clint-mswi > + - const: thead,c900-clint-mswi > - items: > - const: sifive,clint0 > - const: riscv,clint0 > @@ -74,4 +82,22 @@ examples: > <&cpu4intc 3>, <&cpu4intc 7>; > reg = <0x2000000 0x10000>; > }; > + - | > + clint-mtimer@ac010000 { > + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; > + interrupts-extended = <&cpu1intc 7>, > + <&cpu2intc 7>, > + <&cpu3intc 7>, > + <&cpu4intc 7>; > + reg = <0xac010000 0x00007ff8>; > + }; > + - | > + clint-mswi@94000000 { > + compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi"; > + interrupts-extended = <&cpu1intc 3>, > + <&cpu2intc 3>, > + <&cpu3intc 3>, > + <&cpu4intc 3>; > + reg = <0x94000000 0x00004000>; > + }; > ... > -- > 2.25.1 >
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index a0185e15a42f..2a86b80c3f1e 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -39,6 +39,14 @@ properties: - allwinner,sun20i-d1-clint - thead,th1520-clint - const: thead,c900-clint + - items: + - enum: + - sophgo,sg2042-clint-mtimer + - const: thead,c900-clint-mtimer + - items: + - enum: + - sophgo,sg2042-clint-mswi + - const: thead,c900-clint-mswi - items: - const: sifive,clint0 - const: riscv,clint0 @@ -74,4 +82,22 @@ examples: <&cpu4intc 3>, <&cpu4intc 7>; reg = <0x2000000 0x10000>; }; + - | + clint-mtimer@ac010000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + interrupts-extended = <&cpu1intc 7>, + <&cpu2intc 7>, + <&cpu3intc 7>, + <&cpu4intc 7>; + reg = <0xac010000 0x00007ff8>; + }; + - | + clint-mswi@94000000 { + compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi"; + interrupts-extended = <&cpu1intc 3>, + <&cpu2intc 3>, + <&cpu3intc 3>, + <&cpu4intc 3>; + reg = <0x94000000 0x00004000>; + }; ...