Show patches with: Submitter = Bin Meng       |    State = Action Required       |   148 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v3,11/16] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC [v3,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-11 Bin Meng New
[v3,10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC [v3,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 3 - --- 2022-12-11 Bin Meng New
[v3,09/16] hw/intc: sifive_plic: Update "num-sources" property default value [v3,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 1 - --- 2022-12-11 Bin Meng New
[v3,08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic… [v3,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-11 Bin Meng New
[v3,07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser [v3,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC 1 - - --- 2022-12-11 Bin Meng New
[v3,06/16] hw/intc: sifive_plic: Drop PLICMode_H [v3,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-11 Bin Meng New
[v3,05/16] hw/riscv: spike: Remove misleading comments [v3,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-11 Bin Meng New
[v3,04/16] hw/riscv: Sort machines Kconfig options in alphabetical order [v3,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 3 - --- 2022-12-11 Bin Meng New
[v3,03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC [v3,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-11 Bin Meng New
[v3,02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers [v3,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-11 Bin Meng New
[v3,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC [v3,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 3 - --- 2022-12-11 Bin Meng New
[v2,16/16] hw/intc: sifive_plic: Fix the pending register range check [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 1 - --- 2022-12-07 Bin Meng New
[v2,15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 1 - --- 2022-12-07 Bin Meng New
[v2,14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-07 Bin Meng New
[v2,13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 1 - --- 2022-12-07 Bin Meng New
[v2,12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-07 Bin Meng New
[v2,11/16] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-07 Bin Meng New
[v2,10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 3 - --- 2022-12-07 Bin Meng New
[v2,09/16] hw/intc: sifive_plic: Update "num-sources" property default value [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 1 - --- 2022-12-07 Bin Meng New
[v2,08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic… [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-07 Bin Meng New
[v2,07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC 1 - - --- 2022-12-07 Bin Meng New
[v2,06/16] hw/intc: sifive_plic: Drop PLICMode_H [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-07 Bin Meng New
[v2,05/16] hw/riscv: spike: Remove misleading comments [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-07 Bin Meng New
[v2,04/16] hw/riscv: Sort machines Kconfig options in alphabetical order [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 3 - --- 2022-12-07 Bin Meng New
[v2,03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-07 Bin Meng New
[v2,02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-07 Bin Meng New
[v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC [v2,01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 3 - --- 2022-12-07 Bin Meng New
[2/2] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ [1/2] target/riscv: Simplify helper_sret() a little bit - 1 - --- 2022-12-07 Bin Meng New
[1/2] target/riscv: Simplify helper_sret() a little bit [1/2] target/riscv: Simplify helper_sret() a little bit - 2 - --- 2022-12-07 Bin Meng New
target/riscv: Fix mret exception cause when no pmp rule is configured target/riscv: Fix mret exception cause when no pmp rule is configured - 2 - --- 2022-12-05 Bin Meng New
[15/15] hw/intc: sifive_plic: Fix the pending register range check [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 1 - --- 2022-12-01 Bin Meng New
[14/15] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 1 - --- 2022-12-01 Bin Meng New
[13/15] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 1 - --- 2022-12-01 Bin Meng New
[12/15] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 1 - --- 2022-12-01 Bin Meng New
[11/15] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-01 Bin Meng New
[10/15] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-01 Bin Meng New
[09/15] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 3 - --- 2022-12-01 Bin Meng New
[08/15] hw/intc: sifive_plic: Update "num-sources" property default value [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 1 - --- 2022-12-01 Bin Meng New
[07/15] hw/intc: sifive_plic: Improve robustness of the PLIC config parser [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC 1 - - --- 2022-12-01 Bin Meng New
[06/15] hw/intc: sifive_plic: Drop PLICMode_H [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-01 Bin Meng New
[05/15] hw/riscv: spike: Remove misleading comments [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-01 Bin Meng New
[04/15] hw/riscv: Sort machines Kconfig options in alphabetical order [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 1 - --- 2022-12-01 Bin Meng New
[03/15] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 2 - --- 2022-12-01 Bin Meng New
[02/15] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 1 - --- 2022-12-01 Bin Meng New
[01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC - 1 - --- 2022-12-01 Bin Meng New
[v2] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state() [v2] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state() - 1 - --- 2022-11-25 Bin Meng New
target/riscv: Dump sstatus CSR in riscv_cpu_dump_state() target/riscv: Dump sstatus CSR in riscv_cpu_dump_state() - - - --- 2022-11-22 Bin Meng New
treewide: Remove the unnecessary space before semicolon treewide: Remove the unnecessary space before semicolon - 1 - --- 2022-10-24 Bin Meng New
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