diff mbox series

[RFC,27/42] target/mips/translate: Make gen_rdhwr() public

Message ID 20210214175912.732946-28-f4bug@amsat.org (mailing list archive)
State New, archived
Headers show
Series target/mips: Reintroduce the R5900 CPU (with more testing) | expand

Commit Message

Philippe Mathieu-Daudé Feb. 14, 2021, 5:58 p.m. UTC 
We will use gen_rdhwr() outside of translate.c, make it public.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.h | 2 ++
 target/mips/translate.c | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

Comments

Richard Henderson Feb. 15, 2021, 8:51 p.m. UTC | #1 
On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> We will use gen_rdhwr() outside of translate.c, make it public.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.h | 2 ++
>  target/mips/translate.c | 2 +-
>  2 files changed, 3 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
diff mbox series

Patch

diff --git a/target/mips/translate.h b/target/mips/translate.h
index bc91ac4f53f..d2ba3524b51 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -148,6 +148,8 @@  void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
 bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 
+void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel);
+
 extern TCGv cpu_gpr[32], cpu_PC;
 #if defined(TARGET_MIPS64)
 extern TCGv_i64 cpu_gpr_hi[32];
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bed0489997a..c1d07a4591d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -12655,7 +12655,7 @@  static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
     }
 }
 
-static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
+void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
 {
     TCGv t0;