[RFC,30/42] target/mips: Reintroduce the R5900 CPU

Commit Message

Philippe Mathieu-Daudé Feb. 14, 2021, 5:59 p.m. UTC

Now that we have the minimum prerequisites to support the
R5900 CPU, we can reintroduce it.

While we are reverting commit 823f2897bdd ("Disable R5900
support"), we effectively cherry-pick commit ed4f49ba9bb
("target/mips: Define the R5900 CPU").

This reverts commit 823f2897bdd78185f3ba33292a25105ba8bad1b5.

Signed-off-by: Philippe Mathieu-Daudé <[e-mail]>
---
 target/mips/cpu-defs.c.inc | 59 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

Comments

Richard Henderson Feb. 15, 2021, 9:04 p.m. UTC | #1

On 2/14/21 9:59 AM, Philippe Mathieu-Daudé wrote:
> Now that we have the minimum prerequisites to support the
> R5900 CPU, we can reintroduce it.
> 
> While we are reverting commit 823f2897bdd ("Disable R5900
> support"), we effectively cherry-pick commit ed4f49ba9bb
> ("target/mips: Define the R5900 CPU").
> 
> This reverts commit 823f2897bdd78185f3ba33292a25105ba8bad1b5.
> 
> Signed-off-by: Philippe Mathieu-Daudé <[e-mail]>
> ---
>  target/mips/cpu-defs.c.inc | 59 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 59 insertions(+)

Reviewed-by: Richard Henderson <[e-mail]>

r~

Patch

diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index e03b2a998cd..1a73b5409f0 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -411,6 +411,65 @@  const mips_def_t mips_defs[] =
         .insn_flags = CPU_MIPS32R5,
         .mmu_type = MMU_TYPE_R4000,
     },
+    {
+        /*
+         * The Toshiba TX System RISC TX79 Core Architecture manual
+         *
+         * https://wiki.qemu.org/File:C790.pdf
+         *
+         * describes the C790 processor that is a follow-up to the R5900.
+         * There are a few notable differences in that the R5900 FPU
+         *
+         * - is not IEEE 754-1985 compliant,
+         * - does not implement double format, and
+         * - its machine code is nonstandard.
+         */
+        .name = "R5900",
+        .CP0_PRid = 0x00002E00,
+        /* No L2 cache, icache size 32k, dcache size 32k, uncached coherency. */
+        .CP0_Config0 = (0x3 << 9) | (0x3 << 6) | (0x2 << CP0C0_K0),
+        .CP0_Status_rw_bitmask = 0xF4C79C1F,
+#ifdef CONFIG_USER_ONLY
+        /*
+         * R5900 hardware traps to the Linux kernel for IEEE 754-1985 and LL/SC
+         * emulation. For user only, QEMU is the kernel, so we emulate the traps
+         * by simply emulating the instructions directly.
+         *
+         * Note: Config1 is only used internally, the R5900 has only Config0.
+         */
+        .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
+        .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
+        .CP0_LLAddr_shift = 4,
+        .CP1_fcr0 = (0x38 << FCR0_PRID) | (0x0 << FCR0_REV),
+        .CP1_fcr31 = 0,
+        .CP1_fcr31_rw_bitmask = 0x0183FFFF,
+#else
+        /*
+         * The R5900 COP1 FPU implements single-precision floating-point
+         * operations but is not entirely IEEE 754-1985 compatible. In
+         * particular,
+         *
+         * - NaN (not a number) and +/- infinities are not supported;
+         * - exception mechanisms are not fully supported;
+         * - denormalized numbers are not supported;
+         * - rounding towards nearest and +/- infinities are not supported;
+         * - computed results usually differs in the least significant bit;
+         * - saturations can differ more than the least significant bit.
+         *
+         * Since only rounding towards zero is supported, the two least
+         * significant bits of FCR31 are hardwired to 01.
+         *
+         * FPU emulation is disabled here until it is implemented.
+         *
+         * Note: Config1 is only used internally, the R5900 has only Config0.
+         */
+        .CP0_Config1 = (47 << CP0C1_MMU),
+#endif /* !CONFIG_USER_ONLY */
+        .SEGBITS = 32,
+        .PABITS = 32,
+        .insn_flags = CPU_MIPS3 | INSN_R5900 | ASE_MMI,
+        .mmu_type = MMU_TYPE_R4000,
+    },
     {
         /* A generic CPU supporting MIPS32 Release 6 ISA.
            FIXME: Support IEEE 754-2008 FP.