| Message ID | 20221201140811.142123-10-bmeng@tinylab.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC | expand |
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote: > Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003 > supports 52 interrupt sources while G000 supports 51 interrupt > sources. > > We use the value of G002 and G003, so it is 53 (including source 0). > > [1] G000 manual: > https://sifive.cdn.prismic.io/sifive/4faf3e34-4a42-4c2f-be9e-c77baa4928c7_fe310-g000-manual-v3p2.pdf > > [2] G002 manual: > https://sifive.cdn.prismic.io/sifive/034760b5-ac6a-4b1c-911c-f4148bb2c4a5_fe310-g002-v1p5.pdf > > [3] G003 manual: > https://sifive.cdn.prismic.io/sifive/3af39c59-6498-471e-9dab-5355a0d539eb_fe310-g003-manual.pdf > > Fixes: eb637edb1241 ("SiFive Freedom E Series RISC-V Machine") > Signed-off-by: Bin Meng <bmeng@tinylab.org> > --- > > include/hw/riscv/sifive_e.h | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> > diff --git a/include/hw/riscv/sifive_e.h > b/include/hw/riscv/sifive_e.h > index d738745925..9e58247fd8 100644 > --- a/include/hw/riscv/sifive_e.h > +++ b/include/hw/riscv/sifive_e.h > @@ -82,7 +82,12 @@ enum { > }; > > #define SIFIVE_E_PLIC_HART_CONFIG "M" > -#define SIFIVE_E_PLIC_NUM_SOURCES 127 > +/* > + * Freedom E310 G002 and G003 supports 52 interrupt sources while > + * Freedom E310 G000 supports 51 interrupt sources. We use the value > + * of G002 and G003, so it is 53 (including interrupt source 0). > + */ > +#define SIFIVE_E_PLIC_NUM_SOURCES 53 > #define SIFIVE_E_PLIC_NUM_PRIORITIES 7 > #define SIFIVE_E_PLIC_PRIORITY_BASE 0x04 > #define SIFIVE_E_PLIC_PENDING_BASE 0x1000
On Fri, Dec 2, 2022 at 12:12 AM Bin Meng <bmeng@tinylab.org> wrote: > > Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003 > supports 52 interrupt sources while G000 supports 51 interrupt sources. > > We use the value of G002 and G003, so it is 53 (including source 0). > > [1] G000 manual: > https://sifive.cdn.prismic.io/sifive/4faf3e34-4a42-4c2f-be9e-c77baa4928c7_fe310-g000-manual-v3p2.pdf > > [2] G002 manual: > https://sifive.cdn.prismic.io/sifive/034760b5-ac6a-4b1c-911c-f4148bb2c4a5_fe310-g002-v1p5.pdf > > [3] G003 manual: > https://sifive.cdn.prismic.io/sifive/3af39c59-6498-471e-9dab-5355a0d539eb_fe310-g003-manual.pdf > > Fixes: eb637edb1241 ("SiFive Freedom E Series RISC-V Machine") > Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > include/hw/riscv/sifive_e.h | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h > index d738745925..9e58247fd8 100644 > --- a/include/hw/riscv/sifive_e.h > +++ b/include/hw/riscv/sifive_e.h > @@ -82,7 +82,12 @@ enum { > }; > > #define SIFIVE_E_PLIC_HART_CONFIG "M" > -#define SIFIVE_E_PLIC_NUM_SOURCES 127 > +/* > + * Freedom E310 G002 and G003 supports 52 interrupt sources while > + * Freedom E310 G000 supports 51 interrupt sources. We use the value > + * of G002 and G003, so it is 53 (including interrupt source 0). > + */ > +#define SIFIVE_E_PLIC_NUM_SOURCES 53 > #define SIFIVE_E_PLIC_NUM_PRIORITIES 7 > #define SIFIVE_E_PLIC_PRIORITY_BASE 0x04 > #define SIFIVE_E_PLIC_PENDING_BASE 0x1000 > -- > 2.34.1 > >
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index d738745925..9e58247fd8 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -82,7 +82,12 @@ enum { }; #define SIFIVE_E_PLIC_HART_CONFIG "M" -#define SIFIVE_E_PLIC_NUM_SOURCES 127 +/* + * Freedom E310 G002 and G003 supports 52 interrupt sources while + * Freedom E310 G000 supports 51 interrupt sources. We use the value + * of G002 and G003, so it is 53 (including interrupt source 0). + */ +#define SIFIVE_E_PLIC_NUM_SOURCES 53 #define SIFIVE_E_PLIC_NUM_PRIORITIES 7 #define SIFIVE_E_PLIC_PRIORITY_BASE 0x04 #define SIFIVE_E_PLIC_PENDING_BASE 0x1000
Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003 supports 52 interrupt sources while G000 supports 51 interrupt sources. We use the value of G002 and G003, so it is 53 (including source 0). [1] G000 manual: https://sifive.cdn.prismic.io/sifive/4faf3e34-4a42-4c2f-be9e-c77baa4928c7_fe310-g000-manual-v3p2.pdf [2] G002 manual: https://sifive.cdn.prismic.io/sifive/034760b5-ac6a-4b1c-911c-f4148bb2c4a5_fe310-g002-v1p5.pdf [3] G003 manual: https://sifive.cdn.prismic.io/sifive/3af39c59-6498-471e-9dab-5355a0d539eb_fe310-g003-manual.pdf Fixes: eb637edb1241 ("SiFive Freedom E Series RISC-V Machine") Signed-off-by: Bin Meng <bmeng@tinylab.org> --- include/hw/riscv/sifive_e.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)