| Message ID | 20221201140811.142123-8-bmeng@tinylab.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC | expand |
On Fri, Dec 2, 2022 at 12:12 AM Bin Meng <bmeng@tinylab.org> wrote: > > At present the default value of "num-sources" property is zero, > which does not make a lot of sense, as in sifive_plic_realize() > we see s->bitfield_words is calculated by: > > s->bitfield_words = (s->num_sources + 31) >> 5; > > if the we don't configure "num-sources" property its default value > zero makes s->bitfield_words zero too, which isn't true because > interrupt source 0 still occupies one word. > > Let's change the default value to 1 meaning that only interrupt > source 0 is supported by default and a sanity check in realize(). > > While we are here, add a comment to describe the exact meaning of > this property that the number should include interrupt source 0. > A wrong multi-line comment format is corrected too. > > Signed-off-by: Bin Meng <bmeng@tinylab.org> > --- > > hw/intc/sifive_plic.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c > index 5fd9a53569..2bd292410d 100644 > --- a/hw/intc/sifive_plic.c > +++ b/hw/intc/sifive_plic.c > @@ -363,6 +363,11 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp) > > parse_hart_config(s); > > + if (!s->num_sources) { > + error_report("plic: invalid number of interrupt sources"); We should propagate the error up via errp instead Otherwise: Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > + exit(1); > + } > + > s->bitfield_words = (s->num_sources + 31) >> 5; > s->num_enables = s->bitfield_words * s->num_addrs; > s->source_priority = g_new0(uint32_t, s->num_sources); > @@ -379,7 +384,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp) > s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts); > qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts); > > - /* We can't allow the supervisor to control SEIP as this would allow the > + /* > + * We can't allow the supervisor to control SEIP as this would allow the > * supervisor to clear a pending external interrupt which will result in > * lost a interrupt in the case a PLIC is attached. The SEIP bit must be > * hardware controlled when a PLIC is attached. > @@ -419,7 +425,8 @@ static const VMStateDescription vmstate_sifive_plic = { > static Property sifive_plic_properties[] = { > DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config), > DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0), > - DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0), > + /* number of interrupt sources including interrupt source 0 */ > + DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1), > DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0), > DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0), > DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0), > -- > 2.34.1 > >
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 5fd9a53569..2bd292410d 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -363,6 +363,11 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp) parse_hart_config(s); + if (!s->num_sources) { + error_report("plic: invalid number of interrupt sources"); + exit(1); + } + s->bitfield_words = (s->num_sources + 31) >> 5; s->num_enables = s->bitfield_words * s->num_addrs; s->source_priority = g_new0(uint32_t, s->num_sources); @@ -379,7 +384,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp) s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts); qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts); - /* We can't allow the supervisor to control SEIP as this would allow the + /* + * We can't allow the supervisor to control SEIP as this would allow the * supervisor to clear a pending external interrupt which will result in * lost a interrupt in the case a PLIC is attached. The SEIP bit must be * hardware controlled when a PLIC is attached. @@ -419,7 +425,8 @@ static const VMStateDescription vmstate_sifive_plic = { static Property sifive_plic_properties[] = { DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config), DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0), - DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0), + /* number of interrupt sources including interrupt source 0 */ + DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1), DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0), DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0), DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
At present the default value of "num-sources" property is zero, which does not make a lot of sense, as in sifive_plic_realize() we see s->bitfield_words is calculated by: s->bitfield_words = (s->num_sources + 31) >> 5; if the we don't configure "num-sources" property its default value zero makes s->bitfield_words zero too, which isn't true because interrupt source 0 still occupies one word. Let's change the default value to 1 meaning that only interrupt source 0 is supported by default and a sanity check in realize(). While we are here, add a comment to describe the exact meaning of this property that the number should include interrupt source 0. A wrong multi-line comment format is corrected too. Signed-off-by: Bin Meng <bmeng@tinylab.org> --- hw/intc/sifive_plic.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)