@@ -163,7 +163,7 @@ static int gicv3_its_wait_commands(struct host_its *hw_its)
static uint64_t encode_rdbase(struct host_its *hw_its, unsigned int cpu,
uint64_t reg)
{
- reg &= ~GENMASK(51, 16);
+ reg &= ~GENMASK_ULL(51, 16);
reg |= gicv3_get_redist_address(cpu, hw_its->flags & HOST_ITS_USES_PTA);
@@ -219,7 +219,7 @@ static int its_send_cmd_mapd(struct host_its *its, uint32_t deviceid,
{
ASSERT(size_bits <= its->evid_bits);
ASSERT(size_bits > 0);
- ASSERT(!(itt_addr & ~GENMASK(51, 8)));
+ ASSERT(!(itt_addr & ~GENMASK_ULL(51, 8)));
/* The number of events is encoded as "number of bits minus one". */
size_bits--;
@@ -273,9 +273,9 @@ int gicv3_its_setup_collection(unsigned int cpu)
#define BASER_ATTR_MASK \
((0x3UL << GITS_BASER_SHAREABILITY_SHIFT) | \
- (0x7UL << GITS_BASER_OUTER_CACHEABILITY_SHIFT) | \
- (0x7UL << GITS_BASER_INNER_CACHEABILITY_SHIFT))
-#define BASER_RO_MASK (GENMASK(58, 56) | GENMASK(52, 48))
+ (0x7ULL << GITS_BASER_OUTER_CACHEABILITY_SHIFT) | \
+ (0x7ULL << GITS_BASER_INNER_CACHEABILITY_SHIFT))
+#define BASER_RO_MASK (GENMASK_ULL(58, 56) | GENMASK_ULL(52, 48))
/* Check that the physical address can be encoded in the PROPBASER register. */
static bool check_baser_phys_addr(void *vaddr, unsigned int page_bits)
@@ -287,13 +287,13 @@ static bool check_baser_phys_addr(void *vaddr, unsigned int page_bits)
static uint64_t encode_baser_phys_addr(paddr_t addr, unsigned int page_bits)
{
- uint64_t ret = addr & GENMASK(47, page_bits);
+ uint64_t ret = addr & GENMASK_ULL(47, page_bits);
if ( page_bits < 16 )
return ret;
/* For 64K pages address bits 51-48 are encoded in bits 15-12. */
- return ret | ((addr & GENMASK(51, 48)) >> (48 - 12));
+ return ret | ((addr & GENMASK_ULL(51, 48)) >> (48 - 12));
}
static void *its_map_cbaser(struct host_its *its)
@@ -310,7 +310,7 @@ static void *its_map_cbaser(struct host_its *its)
if ( !buffer )
return NULL;
- if ( virt_to_maddr(buffer) & ~GENMASK(51, 12) )
+ if ( virt_to_maddr(buffer) & ~GENMASK_ULL(51, 12) )
{
xfree(buffer);
return NULL;
@@ -446,7 +446,7 @@ static int gicv3_disable_its(struct host_its *hw_its)
udelay(1);
} while ( NOW() <= deadline );
- printk(XENLOG_ERR "ITS@%lx not quiescent.\n", hw_its->addr);
+ printk(XENLOG_ERR "ITS@%" PRIu64 " not quiescent.\n", hw_its->addr);
return -ETIMEDOUT;
}
@@ -999,7 +999,7 @@ static void add_to_host_its_list(paddr_t addr, paddr_t size,
its_data->size = size;
its_data->dt_node = node;
- printk("GICv3: Found ITS @0x%lx\n", addr);
+ printk("GICv3: Found ITS 0x%" PRIu64 "\n", addr);
list_add_tail(&its_data->entry, &host_its_list);
}
@@ -134,7 +134,7 @@ void gicv3_set_redist_address(paddr_t address, unsigned int redist_id)
uint64_t gicv3_get_redist_address(unsigned int cpu, bool use_pta)
{
if ( use_pta )
- return per_cpu(lpi_redist, cpu).redist_addr & GENMASK(51, 16);
+ return per_cpu(lpi_redist, cpu).redist_addr & GENMASK_ULL(51, 16);
else
return per_cpu(lpi_redist, cpu).redist_id << 16;
}
@@ -253,7 +253,7 @@ static int gicv3_lpi_allocate_pendtable(unsigned int cpu)
return -ENOMEM;
/* Make sure the physical address can be encoded in the register. */
- if ( virt_to_maddr(pendtable) & ~GENMASK(51, 16) )
+ if ( virt_to_maddr(pendtable) & ~GENMASK_ULL(51, 16) )
{
xfree(pendtable);
return -ERANGE;
@@ -281,7 +281,7 @@ static int gicv3_lpi_set_pendtable(void __iomem *rdist_base)
return -ENOMEM;
}
- ASSERT(!(virt_to_maddr(pendtable) & ~GENMASK(51, 16)));
+ ASSERT(!(virt_to_maddr(pendtable) & ~GENMASK_ULL(51, 16)));
val = GIC_BASER_CACHE_RaWaWb << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT;
val |= GIC_BASER_CACHE_SameAsInner << GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT;
@@ -329,7 +329,7 @@ static int gicv3_lpi_set_proptable(void __iomem * rdist_base)
return -ENOMEM;
/* Make sure the physical address can be encoded in the register. */
- if ( (virt_to_maddr(table) & ~GENMASK(51, 12)) )
+ if ( (virt_to_maddr(table) & ~GENMASK_ULL(51, 12)) )
{
xfree(table);
return -ERANGE;
@@ -417,12 +417,12 @@ static void gicv3_dump_state(const struct vcpu *v)
if ( v == current )
{
for ( i = 0; i < gicv3_info.nr_lrs; i++ )
- printk(" HW_LR[%d]=%llx\n", i, gicv3_ich_read_lr(i));
+ printk(" HW_LR[%d]=%" PRIu64 "\n", i, gicv3_ich_read_lr(i));
}
else
{
for ( i = 0; i < gicv3_info.nr_lrs; i++ )
- printk(" VCPU_LR[%d]=%llx\n", i, v->arch.gic.v3.lr[i]);
+ printk(" VCPU_LR[%d]=%" PRIu64 "\n", i, v->arch.gic.v3.lr[i]);
}
}
@@ -195,7 +195,7 @@
#define ICH_SGI_IRQMODE_SHIFT 40
#define ICH_SGI_IRQMODE_MASK 0x1
-#define ICH_SGI_TARGET_OTHERS 1UL
+#define ICH_SGI_TARGET_OTHERS 1ULL
#define ICH_SGI_TARGET_LIST 0
#define ICH_SGI_IRQ_SHIFT 24
#define ICH_SGI_IRQ_MASK 0xf
@@ -38,7 +38,7 @@
#define GITS_PIDR2 GICR_PIDR2
/* Register bits */
-#define GITS_VALID_BIT BIT(63, UL)
+#define GITS_VALID_BIT BIT(63, ULL)
#define GITS_CTLR_QUIESCENT BIT(31, UL)
#define GITS_CTLR_ENABLE BIT(0, UL)
@@ -96,13 +96,13 @@ typedef uint16_t coll_table_entry_t;
* in the lowest 5 bits of the word.
*/
typedef uint64_t dev_table_entry_t;
-#define DEV_TABLE_ITT_ADDR(x) ((x) & GENMASK(51, 8))
+#define DEV_TABLE_ITT_ADDR(x) ((x) & GENMASK_ULL(51, 8))
#define DEV_TABLE_ITT_SIZE(x) (BIT(((x) & GENMASK(4, 0)) + 1, UL))
#define DEV_TABLE_ENTRY(addr, bits) \
(((addr) & GENMASK(51, 8)) | (((bits) - 1) & GENMASK(4, 0)))
#define GITS_BASER_RO_MASK (GITS_BASER_TYPE_MASK | \
- (0x1fL << GITS_BASER_ENTRY_SIZE_SHIFT))
+ (0x1fLL << GITS_BASER_ENTRY_SIZE_SHIFT))
/*
* The physical address is encoded slightly differently depending on
@@ -112,10 +112,10 @@ typedef uint64_t dev_table_entry_t;
static paddr_t get_baser_phys_addr(uint64_t reg)
{
if ( reg & BIT(9, UL) )
- return (reg & GENMASK(47, 16)) |
+ return (reg & GENMASK_ULL(47, 16)) |
((reg & GENMASK(15, 12)) << 36);
else
- return reg & GENMASK(47, 12);
+ return reg & GENMASK_ULL(47, 12);
}
/* Must be called with the ITS lock held. */
@@ -414,7 +414,7 @@ static int update_lpi_property(struct domain *d, struct pending_irq *p)
if ( !d->arch.vgic.rdists_enabled )
return 0;
- addr = d->arch.vgic.rdist_propbase & GENMASK(51, 12);
+ addr = d->arch.vgic.rdist_propbase & GENMASK_ULL(51, 12);
ret = access_guest_memory_by_ipa(d, addr + p->irq - LPI_OFFSET,
&property, sizeof(property), false);
@@ -897,7 +897,8 @@ out_unlock:
static void dump_its_command(uint64_t *command)
{
- gdprintk(XENLOG_WARNING, " cmd 0x%02lx: %016lx %016lx %016lx %016lx\n",
+ gdprintk(XENLOG_WARNING, " cmd 0x%" PRIu64 ": %" PRIu64
+ "%" PRIu64 "%" PRIu64 "%" PRIu64 "\n",
its_cmd_get_command(command),
command[0], command[1], command[2], command[3]);
}
@@ -909,7 +910,7 @@ static void dump_its_command(uint64_t *command)
*/
static int vgic_its_handle_cmds(struct domain *d, struct virt_its *its)
{
- paddr_t addr = its->cbaser & GENMASK(51, 12);
+ paddr_t addr = its->cbaser & GENMASK_ULL(51, 12);
uint64_t command[4];
ASSERT(spin_is_locked(&its->vcmd_lock));
@@ -1122,7 +1123,7 @@ read_as_zero_64:
read_impl_defined:
printk(XENLOG_G_DEBUG
- "%pv: vGITS: RAZ on implementation defined register offset %#04lx\n",
+ "%pv: vGITS: RAZ on implementation defined register offset %" PRIx64 "#04llx\n",
v, info->gpa & 0xffff);
*r = 0;
return 1;
"unsigned long long" is defined as 64 bits on AArch64 and AArch32 Thus, one should this instead of "unsigned long" which is 32 bits on AArch32. Also use 'PRIu64' instead of 'lx' to print uint64_t. Signed-off-by: Ayan Kumar Halder <ayankuma@amd.com> --- xen/arch/arm/gic-v3-its.c | 20 ++++++++++---------- xen/arch/arm/gic-v3-lpi.c | 8 ++++---- xen/arch/arm/gic-v3.c | 4 ++-- xen/arch/arm/include/asm/gic_v3_defs.h | 2 +- xen/arch/arm/include/asm/gic_v3_its.h | 2 +- xen/arch/arm/vgic-v3-its.c | 17 +++++++++-------- 6 files changed, 27 insertions(+), 26 deletions(-)