diff mbox series

[RFC,v1,06/12] Arm: GICv3: Emulate of ICC_SGI1R on AArch32

Message ID 20221021153128.44226-7-ayankuma@amd.com (mailing list archive)
State New, archived
Headers show
Series Arm: Enable GICv3 for AArch32 | expand

Commit Message

Ayan Kumar Halder Oct. 21, 2022, 3:31 p.m. UTC 
Refer Arm IHI 0069H ID020922, 12.5.23, ICC_SGI1R is a 64 bit register on
Aarch32 systems. Thus, the prototype needs to change to reflect this.

Signed-off-by: Ayan Kumar Halder <ayankuma@amd.com>
---
 xen/arch/arm/vgic-v3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Julien Grall Oct. 22, 2022, 10:46 a.m. UTC | #1 
Title: Similar to the previous patch, you are fixing the existing emulation.

On 21/10/2022 16:31, Ayan Kumar Halder wrote:
> Refer Arm IHI 0069H ID020922, 12.5.23, ICC_SGI1R is a 64 bit register on
> Aarch32 systems. Thus, the prototype needs to change to reflect this.
At first, it wasn't obvious why changing the prototype is enough. So it 
would be good to explain it in the commit message.

> 
> Signed-off-by: Ayan Kumar Halder <ayankuma@amd.com>
> ---
>   xen/arch/arm/vgic-v3.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
> index 9f31360f56..48e8ef95d2 100644
> --- a/xen/arch/arm/vgic-v3.c
> +++ b/xen/arch/arm/vgic-v3.c
> @@ -1482,7 +1482,7 @@ write_reserved:
>       return 1;
>   }
>   
> -static bool vgic_v3_to_sgi(struct vcpu *v, register_t sgir)
> +static bool vgic_v3_to_sgi(struct vcpu *v, uint64_t sgir)
>   {
>       int virq;
>       int irqmode;

Cheers,
diff mbox series

Patch

diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index 9f31360f56..48e8ef95d2 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -1482,7 +1482,7 @@  write_reserved:
     return 1;
 }
 
-static bool vgic_v3_to_sgi(struct vcpu *v, register_t sgir)
+static bool vgic_v3_to_sgi(struct vcpu *v, uint64_t sgir)
 {
     int virq;
     int irqmode;