| Message ID | 20221021153128.44226-2-ayankuma@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Arm: Enable GICv3 for AArch32 | expand |
Hi Ayan, On 21/10/2022 16:31, Ayan Kumar Halder wrote: > Refer ARM DDI 0487G.b ID072021, EC==0b011000 is supported for Aarch64 state > only. This is when MSR, MRS, System instruction execution in AArch64 state > is trapped, that is not reported using EC 0b000000, 0b000001 or 0b000111. I don't understand the second sentence. However, what matter here is the fact the system registers are 64-bit only. The change itself, looks ok to me. Cheers,
diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 0c23f6df9d..c31140eb20 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1520,6 +1520,7 @@ static bool vgic_v3_emulate_sgi1r(struct cpu_user_regs *regs, uint64_t *r, } } +#ifdef CONFIG_ARM_64 static bool vgic_v3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr) { struct hsr_sysreg sysreg = hsr.sysreg; @@ -1540,6 +1541,7 @@ static bool vgic_v3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr) return false; } } +#endif static bool vgic_v3_emulate_cp64(struct cpu_user_regs *regs, union hsr hsr) { @@ -1563,8 +1565,10 @@ static bool vgic_v3_emulate_reg(struct cpu_user_regs *regs, union hsr hsr) { switch (hsr.ec) { +#ifdef CONFIG_ARM_64 case HSR_EC_SYSREG: return vgic_v3_emulate_sysreg(regs, hsr); +#endif case HSR_EC_CP15_64: return vgic_v3_emulate_cp64(regs, hsr); default:
Refer ARM DDI 0487G.b ID072021, EC==0b011000 is supported for Aarch64 state only. This is when MSR, MRS, System instruction execution in AArch64 state is trapped, that is not reported using EC 0b000000, 0b000001 or 0b000111. Signed-off-by: Ayan Kumar Halder <ayankuma@amd.com> --- xen/arch/arm/vgic-v3.c | 4 ++++ 1 file changed, 4 insertions(+)