Show patches with: Submitter = Alistair Francis       |    State = Action Required       |   724 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,18/65] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions 2 2 - --- 2024-01-10 Alistair Francis New
[PULL,17/65] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions 2 2 - --- 2024-01-10 Alistair Francis New
[PULL,16/65] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions 2 2 - --- 2024-01-10 Alistair Francis New
[PULL,15/65] hw/riscv: virt: Make few IMSIC macros and functions public [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions 1 3 - --- 2024-01-10 Alistair Francis New
[PULL,14/65] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions 2 - - --- 2024-01-10 Alistair Francis New
[PULL,13/65] hw/arm/virt-acpi-build.c: Migrate virtio creation to common location [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions 1 2 - --- 2024-01-10 Alistair Francis New
[PULL,12/65] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions 1 3 - --- 2024-01-10 Alistair Francis New
[PULL,11/65] target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong() [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions - 1 - --- 2024-01-10 Alistair Francis New
[PULL,10/65] target/riscv/kvm: add RISCV_CONFIG_REG() [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions - 1 - --- 2024-01-10 Alistair Francis New
[PULL,09/65] target/riscv/kvm: change timer regs size to u64 [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions - 1 - --- 2024-01-10 Alistair Francis New
[PULL,08/65] target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64 [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions - 1 - --- 2024-01-10 Alistair Francis New
[PULL,07/65] target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32 [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions - 1 - --- 2024-01-10 Alistair Francis New
[PULL,06/65] target/riscv/cpu.c: fix machine IDs getters [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions - 2 - --- 2024-01-10 Alistair Francis New
[PULL,05/65] target/riscv/pmp: Use hwaddr instead of target_ulong for RV32 [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions - 1 - --- 2024-01-10 Alistair Francis New
[PULL,04/65] target/riscv: Not allow write mstatus_vs without RVV [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions - 1 - --- 2024-01-10 Alistair Francis New
[PULL,03/65] target/riscv: Fix th.dcache.cval1 priviledge check [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions - 2 - --- 2024-01-10 Alistair Francis New
[PULL,02/65] target/riscv: The whole vector register move instructions depend on vsew [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions 1 - - --- 2024-01-10 Alistair Francis New
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions - 1 - --- 2024-01-10 Alistair Francis New
[PULL,00/65] riscv-to-apply queue - - - --- 2024-01-10 Alistair Francis New
[3/3] target/riscv: Ensure mideleg is set correctly on reset target/riscv: A few bug fixes and Coverity fix - 1 - --- 2024-01-08 Alistair Francis New
[2/3] target/riscv: Don't adjust vscause for exceptions target/riscv: A few bug fixes and Coverity fix - 1 - --- 2024-01-08 Alistair Francis New
[1/3] target/riscv: Assert that the CSR numbers will be correct target/riscv: A few bug fixes and Coverity fix - 1 - --- 2024-01-08 Alistair Francis New
[v3,3/3] hw/nvme: Add SPDM over DOE support Initial support for SPDM Responders 1 1 - --- 2023-11-23 Alistair Francis New
[v3,2/3] backends: Initial support for SPDM socket support Initial support for SPDM Responders - - - --- 2023-11-23 Alistair Francis New
[v3,1/3] hw/pci: Add all Data Object Types defined in PCIe r6.0 Initial support for SPDM Responders - 1 - --- 2023-11-23 Alistair Francis New
[PULL,6/6] target/riscv/cpu_helper.c: Fix mxr bit behavior [PULL,1/6] linux-user/riscv: Add Zicboz block size to hwprobe - 2 - --- 2023-11-22 Alistair Francis New
[PULL,5/6] target/riscv/cpu_helper.c: Invalid exception on MMU translation stage [PULL,1/6] linux-user/riscv: Add Zicboz block size to hwprobe - 2 - --- 2023-11-22 Alistair Francis New
[PULL,4/6] riscv: Fix SiFive E CLINT clock frequency [PULL,1/6] linux-user/riscv: Add Zicboz block size to hwprobe - 2 - --- 2023-11-22 Alistair Francis New
[PULL,3/6] target/riscv: don't verify ISA compatibility for zicntr and zihpm [PULL,1/6] linux-user/riscv: Add Zicboz block size to hwprobe - 2 - --- 2023-11-22 Alistair Francis New
[PULL,2/6] hw/riscv/virt.c: do create_fdt() earlier, add finalize_fdt() [PULL,1/6] linux-user/riscv: Add Zicboz block size to hwprobe - 1 - --- 2023-11-22 Alistair Francis New
[PULL,1/6] linux-user/riscv: Add Zicboz block size to hwprobe [PULL,1/6] linux-user/riscv: Add Zicboz block size to hwprobe - 2 - --- 2023-11-22 Alistair Francis New
[PULL,0/6] riscv-to-apply queue - - - --- 2023-11-22 Alistair Francis New
[PULL,49/49] docs/about/deprecated: Document RISC-V "pmu-num" deprecation [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei 1 2 - --- 2023-11-07 Alistair Francis New
[PULL,48/49] target/riscv: Add "pmu-mask" property to replace "pmu-num" [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,47/49] target/riscv: Use existing PMU counter mask in FDT generation [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 3 - --- 2023-11-07 Alistair Francis New
[PULL,46/49] target/riscv: Don't assume PMU counters are continuous [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 3 - --- 2023-11-07 Alistair Francis New
[PULL,45/49] target/riscv: Propagate error from PMU setup [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 3 - --- 2023-11-07 Alistair Francis New
[PULL,44/49] target/riscv: cpu: Set the OpenTitan priv to 1.12.0 [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,43/49] hw/ssi: ibex_spi_host: Clear the interrupt even if disabled [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,42/49] disas/riscv: Replace TABs with space [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei 1 - - --- 2023-11-07 Alistair Francis New
[PULL,41/49] disas/riscv: Add support for vector crypto extensions [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - - - --- 2023-11-07 Alistair Francis New
[PULL,40/49] disas/riscv: Add rv_codec_vror_vi for vror.vi [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei 1 - - --- 2023-11-07 Alistair Francis New
[PULL,39/49] disas/riscv: Add rv_fmt_vd_vs2_uimm format [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei 1 - - --- 2023-11-07 Alistair Francis New
[PULL,38/49] target/riscv: Move vector crypto extensions to riscv_cpu_extensions [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei 1 1 - --- 2023-11-07 Alistair Francis New
[PULL,37/49] target/riscv: Expose Zvks[c|g] extnesion properties [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei 1 1 - --- 2023-11-07 Alistair Francis New
[PULL,36/49] target/riscv: Add cfg properties for Zvks[c|g] extensions [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei 1 1 - --- 2023-11-07 Alistair Francis New
[PULL,35/49] target/riscv: Expose Zvkn[c|g] extnesion properties [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei 1 1 - --- 2023-11-07 Alistair Francis New
[PULL,34/49] target/riscv: Add cfg properties for Zvkn[c|g] extensions [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei 1 1 - --- 2023-11-07 Alistair Francis New
[PULL,33/49] target/riscv: Expose Zvkb extension property [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei 1 1 - --- 2023-11-07 Alistair Francis New
[PULL,32/49] target/riscv: Replace Zvbb checking by Zvkb [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,31/49] target/riscv: Add cfg property for Zvkb extension [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei 1 1 - --- 2023-11-07 Alistair Francis New
[PULL,30/49] target/riscv: Expose Zvkt extension property [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei 1 1 - --- 2023-11-07 Alistair Francis New
[PULL,29/49] target/riscv: Add cfg property for Zvkt extension [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei 1 1 - --- 2023-11-07 Alistair Francis New
[PULL,28/49] MAINTAINERS: update mail address for Weiwei Li [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 4 - --- 2023-11-07 Alistair Francis New
[PULL,27/49] target/riscv: correct csr_ops[CSR_MSECCFG] [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,26/49] target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei 1 - - --- 2023-11-07 Alistair Francis New
[PULL,25/49] target/riscv/kvm: add zihpm reg [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,24/49] target/riscv: add zihpm extension flag for TCG [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,23/49] target/riscv/kvm: add zicntr reg [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,22/49] target/riscv: add zicntr extension flag for TCG [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,21/49] target/riscv: pmp: Ignore writes when RW=01 [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,20/49] target/riscv: pmp: Clear pmp/smepmp bits on reset [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,19/49] Add epmp to extensions list and rename it to smepmp [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 2 - --- 2023-11-07 Alistair Francis New
[PULL,18/49] target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,17/49] target/riscv: add riscv_cpu_accelerator_compatible() [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,16/49] target/riscv: handle custom props in qmp_query_cpu_model_expansion [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,15/49] target/riscv/tcg: add tcg_cpu_finalize_features() [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,14/49] qapi,risc-v: add query-cpu-model-expansion [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,13/49] target/riscv/kvm/kvm-cpu.c: add missing property getters() [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,12/49] docs/system/riscv: update 'virt' machine core limit [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,11/49] linux-user/riscv: change default cpu to 'max' [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 3 - --- 2023-11-07 Alistair Francis New
[PULL,10/49] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support. [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,09/49] target/riscv: Add M-mode virtual interrupt and IRQ filtering support. [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,08/49] target/riscv: Split interrupt logic from riscv_cpu_update_mip. [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,07/49] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,06/49] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,05/49] target/riscv: Without H-mode mask all HS mode inturrupts in mie. [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 1 - --- 2023-11-07 Alistair Francis New
[PULL,04/49] target/riscv: rename ext_icboz to ext_zicboz [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 2 - --- 2023-11-07 Alistair Francis New
[PULL,03/49] target/riscv: rename ext_icbom to ext_zicbom [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 2 - --- 2023-11-07 Alistair Francis New
[PULL,02/49] target/riscv: rename ext_icsr to ext_zicsr [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 2 - --- 2023-11-07 Alistair Francis New
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei [PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei - 2 - --- 2023-11-07 Alistair Francis New
[PULL,00/49] riscv-to-apply queue - - - --- 2023-11-07 Alistair Francis New
[2/2] target/riscv: cpu: Set the OpenTitan priv to 1.12.0 RISC-V: OpenTitan: Fixup ePMP and SPI interrupts - 1 - --- 2023-11-02 Alistair Francis New
[1/2] hw/ssi: ibex_spi_host: Clear the interrupt even if disabled RISC-V: OpenTitan: Fixup ePMP and SPI interrupts - 1 - --- 2023-11-02 Alistair Francis New
[v2,3/3] hw/nvme: Add SPDM over DOE support Initial support for SPDM Responders 1 1 - --- 2023-10-17 Alistair Francis New
[v2,2/3] backends: Initial support for SPDM socket support Initial support for SPDM Responders - - - --- 2023-10-17 Alistair Francis New
[v2,1/3] hw/pci: Add all Data Object Types defined in PCIe r6.0 Initial support for SPDM Responders - 1 - --- 2023-10-17 Alistair Francis New
[PULL,54/54] target/riscv: Fix vfwmaccbf16.vf [PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] - 2 - --- 2023-10-12 Alistair Francis New
[PULL,53/54] target/riscv: deprecate capital 'Z' CPU properties [PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] - 2 - --- 2023-10-12 Alistair Francis New
[PULL,52/54] target/riscv: Use env_archcpu for better performance [PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] - 3 - --- 2023-10-12 Alistair Francis New
[PULL,51/54] target/riscv/tcg: remove RVG warning [PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] - 2 - --- 2023-10-12 Alistair Francis New
[PULL,50/54] target/riscv/kvm: support KVM_GET_REG_LIST [PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] 1 1 - --- 2023-10-12 Alistair Francis New
[PULL,49/54] target/riscv/kvm: improve 'init_multiext_cfg' error msg [PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] - 3 - --- 2023-10-12 Alistair Francis New
[PULL,48/54] gdbstub: replace exit calls with proper shutdown for softmmu [PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] - 1 - --- 2023-10-12 Alistair Francis New
[PULL,47/54] hw/char: riscv_htif: replace exit calls with proper shutdown [PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] - 1 - --- 2023-10-12 Alistair Francis New
[PULL,46/54] hw/misc/sifive_test.c: replace exit calls with proper shutdown [PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] - 1 - --- 2023-10-12 Alistair Francis New
[PULL,45/54] softmmu: pass the main loop status to gdb "Wxx" packet [PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] - 1 - --- 2023-10-12 Alistair Francis New
[PULL,44/54] softmmu: add means to pass an exit code when requesting a shutdown [PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] - 1 - --- 2023-10-12 Alistair Francis New
[PULL,43/54] target/riscv/tcg-cpu.c: add extension properties for all cpus [PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] - 1 - --- 2023-10-12 Alistair Francis New
[PULL,42/54] target/riscv: add riscv_cpu_get_name() [PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] - 1 - --- 2023-10-12 Alistair Francis New
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