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Patch Series A/R/T S/W/F Date Submitter Delegate State
drm/i915/cnl: Wa to ignore VBT alternate pin on B-stepping. - - - --- 2017-04-07 Rodrigo Vivi New
drm/i915/cnp: add CNP gmbus support - - - --- 2017-04-07 Rodrigo Vivi New
drm/i915/guc: write wopcm related register once during uc init - 1 - --- 2017-04-07 Daniele Ceraolo Spurio New
[5/5] i915: fence workqueue optimization - - - --- 2017-04-06 Andrea Arcangeli New
[4/5] i915: schedule while freeing the lists of gem objects - - - --- 2017-04-06 Andrea Arcangeli New
[3/5] i915: initialize the free_list of the fencing atomic_helper - - - --- 2017-04-06 Andrea Arcangeli New
[2/5] i915: flush gem obj freeing workqueues to add accuracy to the i915 shrinker - - - --- 2017-04-06 Andrea Arcangeli New
[1/5] i915: avoid kernel hang caused by synchronize rcu struct_mutex deadlock - - - --- 2017-04-06 Andrea Arcangeli New
[0/5] Re: [BUG][REGRESSION] i915 gpu hangs under load - - - --- 2017-04-06 Andrea Arcangeli New
[v6] drm/i915/dp: Validate cached link rate and lane count before retraining - 1 - --- 2017-04-06 Navare, Manasi New
[v5] drm/i915/dp: Validate cached link rate and lane count before retraining - - - --- 2017-04-06 Navare, Manasi New
x86/gpu: CNL uses the same GMS values as SKL 1 - - --- 2017-04-06 Rodrigo Vivi New
[i-g-t,v1] igt_kms: Allow pipes with no cursor plane - - - --- 2017-04-06 Robert Foss New
[67/67] drm/i915/cnl: Adjust min pixel rate. - - - --- 2017-04-06 Rodrigo Vivi New
[66/67] drm/i915/cnl: LSPCON support is gen9+ - - - --- 2017-04-06 Rodrigo Vivi New
[65/67] drm/i915/cnl: Enable Audio Pin Buffer. - - - --- 2017-04-06 Rodrigo Vivi New
[64/67] drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) - 1 - --- 2017-04-06 Rodrigo Vivi New
[63/67] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well. - - - --- 2017-04-06 Rodrigo Vivi New
[62/67] drm/i915/cnl: Add support slice/subslice/eu configs - - - --- 2017-04-06 Rodrigo Vivi New
[61/67] drm/i915/cnl: Setup PAT Index. - 1 - --- 2017-04-06 Rodrigo Vivi New
[60/67] drm/i915/cnl: Enable fifo underrun for Cannonlake. - 1 - --- 2017-04-06 Rodrigo Vivi New
[59/67] drm/i915/cnl: Fix Cannonlake scaler mode programing. - 1 - --- 2017-04-06 Rodrigo Vivi New
[58/67] drm/i915/cnl: Cannonlake color init. - - - --- 2017-04-06 Rodrigo Vivi New
[57/67] x86/gpu: CNL uses the same GMS values as SKL 1 - - --- 2017-04-06 Rodrigo Vivi New
[56/67] drm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake. - - - --- 2017-04-06 Rodrigo Vivi New
[55/67] drm/i915/gen10: implement gen 10 watermarks calculations - - - --- 2017-04-06 Rodrigo Vivi New
[54/67] drm/i915/gen10: fix WM latency printing - - - --- 2017-04-06 Rodrigo Vivi New
[53/67] drm/i915/cnl: don't apply the GEN9/CNL:A WM WAs to CNL:B+ - - - --- 2017-04-06 Rodrigo Vivi New
[52/67] drm/i915/gen10: fix the gen 10 SAGV block time - - - --- 2017-04-06 Rodrigo Vivi New
[51/67] drm/i915/cnl: Enable SAGV for Cannonlake. - - - --- 2017-04-06 Rodrigo Vivi New
[50/67] drm/i915/gen10+: use the SKL code for reading WM latencies - - - --- 2017-04-06 Rodrigo Vivi New
[49/67] drm/i915/cnl: Avoid old DDI translation functions on Cannonlake. - - - --- 2017-04-06 Rodrigo Vivi New
[48/67] drm/i915/cnl: Get DDI clock based on PLLs. - 1 - --- 2017-04-06 Rodrigo Vivi New
[47/67] drm/i915/cnl: Dump the right pll registers when dumping pipe config. - - - --- 2017-04-06 Rodrigo Vivi New
[46/67] drm/i915/cnl: Add allowed DP rates for Cannonlake. - - - --- 2017-04-06 Rodrigo Vivi New
[45/67] drm/i915/cnl: Add max allowed Cannonlake DC. - - - --- 2017-04-06 Rodrigo Vivi New
[44/67] drm/i915/cnl: DC3 to DC5 counters available on CNL. - - - --- 2017-04-06 Rodrigo Vivi New
[43/67] drm/i915: Use HAS_CSR instead of gen number on DMC load. - 1 - --- 2017-04-06 Rodrigo Vivi New
[42/67] drm/i915/DMC/CNL: Load DMC on CNL - 1 - --- 2017-04-06 Rodrigo Vivi New
[41/67] drm/i915/cnl: Add slice and subslice information to debugfs. - - - --- 2017-04-06 Rodrigo Vivi New
[40/67] drm/i915/cnl: Enable loadgen_select bit for vswing sequence - - - --- 2017-04-06 Rodrigo Vivi New
[39/67] drm/i915/cnl: Implement voltage swing sequence. - - - --- 2017-04-06 Rodrigo Vivi New
[38/67] drm/i915/cnl: Add DDI Buffer translation tables for Cannonlake. - - - --- 2017-04-06 Rodrigo Vivi New
[37/67] drm/i915/cnl: Add registers related to voltage swing sequences. - - - --- 2017-04-06 Rodrigo Vivi New
[36/67] drm/i915: Add MMIO helper for 6 ports with different offsets. - - - --- 2017-04-06 Rodrigo Vivi New
[35/67] drm/i915/cnl: Enable wrpll computation for CNL - - - --- 2017-04-06 Rodrigo Vivi New
[34/67] drm/i915/cnl: Initialize PLLs - 1 - --- 2017-04-06 Rodrigo Vivi New
[33/67] drm/i915: Configure DPLL's for Cannonlake - 1 - --- 2017-04-06 Rodrigo Vivi New
[32/67] drm/i915/cnl: DDI - PLL mapping - 1 - --- 2017-04-06 Rodrigo Vivi New
[31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL - - - --- 2017-04-06 Rodrigo Vivi New
[30/67] drm/i915/cnl: Implement CNL display init/unit sequence - - - --- 2017-04-06 Rodrigo Vivi New
[29/67] drm/i915/cnl: Implement .set_cdclk() for CNL - 1 - --- 2017-04-06 Rodrigo Vivi New
[28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL - 1 - --- 2017-04-06 Rodrigo Vivi New
[27/67] drm/i915/cnl: Also need power well sanitize. - 1 - --- 2017-04-06 Rodrigo Vivi New
[26/67] drm/i915/cnl: Add power wells for CNL - 1 - --- 2017-04-06 Rodrigo Vivi New
[25/67] drm/i915/cnl: Inherit RPS stuff from previous platforms. - - - --- 2017-04-06 Rodrigo Vivi New
[24/67] drm/i915/cnl: Add force wake for gen10. - 1 - --- 2017-04-06 Rodrigo Vivi New
[23/67] drm/i915/gen10: Set value of Indirect Context Offset for gen10 - 1 - --- 2017-04-06 Rodrigo Vivi New
[22/67] drm/i915/cnl: Add RT cache flush pipe control w/a - - - --- 2017-04-06 Rodrigo Vivi New
[21/67] drm/i915/cnl: Update the context size - - - --- 2017-04-06 Rodrigo Vivi New
[20/67] drm/i915/cnl: Cannonlake has same MOCS table than Skylake. - 1 - --- 2017-04-06 Rodrigo Vivi New
[19/67] drm/i915/cnl: Configure EU slice power gating. - 1 - --- 2017-04-06 Rodrigo Vivi New
[18/67] drm/i915/cnl: Add initial gen10 golden states. - - - --- 2017-04-06 Rodrigo Vivi New
[17/67] drm/i915/cnl: CNL has an increased DDB size - 1 - --- 2017-04-06 Rodrigo Vivi New
[16/67] drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipe - 2 - --- 2017-04-06 Rodrigo Vivi New
[15/67] drm/i915/cnl: Apply large line width optimization - - - --- 2017-04-06 Rodrigo Vivi New
[14/67] drm/i915/cnl: WaDisableEnhancedSBEVertexCaching - 1 - --- 2017-04-06 Rodrigo Vivi New
[13/67] drm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimization - 1 - --- 2017-04-06 Rodrigo Vivi New
[12/67] drm/i915/cnl: Introduce initial Cannonlake Workarounds. - - - --- 2017-04-06 Rodrigo Vivi New
[11/67] drm/i915/cnl: add IS_CNL_REVID macro - 1 - --- 2017-04-06 Rodrigo Vivi New
[10/67] drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus. - 1 - --- 2017-04-06 Rodrigo Vivi New
[09/67] drm/i915/cnl: Add Cannonlake PCI IDs for U-skus. - 1 - --- 2017-04-06 Rodrigo Vivi New
[08/67] drm/i915/cnl: Cannonlake uses CNP PCH. - 1 - --- 2017-04-06 Rodrigo Vivi New
[07/67] drm/i915/cnl: Introduce Cannonlake platform defition. - 1 - --- 2017-04-06 Rodrigo Vivi New
[06/67] drm/i915/cnp: Panel Power sequence changes for CNP PCH. - 1 - --- 2017-04-06 Rodrigo Vivi New
[05/67] drm/i915/cnp: add CNP gmbus support - 1 - --- 2017-04-06 Rodrigo Vivi New
[04/67] drm/i915/cnp: Add Backlight support to CNP PCH. - - - --- 2017-04-06 Rodrigo Vivi New
[03/67] drm/i915/cnp: Get/set proper Raw clock frequency on CNP. - 1 - --- 2017-04-06 Rodrigo Vivi New
[02/67] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH - 1 - --- 2017-04-06 Rodrigo Vivi New
[01/67] drm/i915/cnp: Introduce Cannonpoint PCH. - 1 - --- 2017-04-06 Rodrigo Vivi New
drm: Take mode_config.mutex in setcrtc ioctl - - - --- 2017-04-06 Daniel Vetter New
drm/atomic: Acquire connection_mutex lock in drm_helper_probe_single_connector_modes, v4. - 1 - --- 2017-04-06 Maarten Lankhorst New
drm: Take mode_config.mutex in setcrtc ioctl - - - --- 2017-04-06 Daniel Vetter New
[v4] drm/i915: Advance ring->head fully when idle - 1 - --- 2017-04-06 Chris Wilson New
[v3] drm/i915: Advance ring->head fully when idle - - - --- 2017-04-06 Chris Wilson New
[2/2] drm/i915: Use wait_for_atomic_us when waiting for gt fifo - 1 - --- 2017-04-06 Mika Kuoppala New
[1/2] drm/i915: Move the GTFIFODBG to the common mmio dbg framework - 1 - --- 2017-04-06 Mika Kuoppala New
[5/5] drm/i915: Use the engine class to get the context size - 1 - --- 2017-04-06 oscar.mateo@intel.com New
[4/5] drm/i915: Split the engine info table in two levels, using class + instance - - - --- 2017-04-06 oscar.mateo@intel.com New
[3/5] drm/i915: Generate the engine name based on the instance number - 1 - --- 2017-04-06 oscar.mateo@intel.com New
[2/5] drm/i915: Use the same vfunc for BSD2 ring init - 1 - --- 2017-04-06 oscar.mateo@intel.com New
[1/5] drm/i915: Classify the engines in class + instance - 1 - --- 2017-04-06 oscar.mateo@intel.com New
[v4,11/11] drm/i915: Implement Link Rate fallback on Link training failure 2 1 - --- 2017-04-06 Jani Nikula New
[v4,10/11] drm/i915/dp: Validate cached link rate and lane count before retraining - - - --- 2017-04-06 Jani Nikula New
[v4,09/11] drm/i915/dp: read sink count to a temporary variable first - 1 - --- 2017-04-06 Jani Nikula New
[v4,08/11] drm/i915/dp: use readb and writeb calls for single byte DPCD access - 1 - --- 2017-04-06 Jani Nikula New
[v4,07/11] drm/i915/dp: localize link rate index variable more - 1 - --- 2017-04-06 Jani Nikula New
[v4,06/11] drm/i915/mst: use max link not sink lane count - 1 - --- 2017-04-06 Jani Nikula New
[v4,05/11] drm/i915/dp: add functions for max common link rate and lane count - 1 - --- 2017-04-06 Jani Nikula New
[v4,04/11] drm/i915/dp: don't call the link parameters sink parameters - 1 - --- 2017-04-06 Jani Nikula New
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