[RFC,v1,114/256] cl8k: add mib.h

Commit Message

Viktor Barna June 17, 2021, 4 p.m. UTC

From: Viktor Barna <[e-mail]>

(Part of the split. Please, take a look at the cover letter for more
details).

Signed-off-by: Viktor Barna <[e-mail]>
---
 drivers/net/wireless/celeno/cl8k/mib.h | 286 +++++++++++++++++++++++++
 1 file changed, 286 insertions(+)
 create mode 100644 drivers/net/wireless/celeno/cl8k/mib.h

--
2.30.0

Patch

diff --git a/drivers/net/wireless/celeno/cl8k/mib.h b/drivers/net/wireless/celeno/cl8k/mib.h
new file mode 100644
index 000000000000..7089ecf3c374
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/mib.h
@@ -0,0 +1,286 @@ 
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_MIB_H
+#define CL_MIB_H
+
+#include "hw.h"
+
+/**
+ * MIB (=Managaement Information Database, 802.11)
+ */
+
+/*
+ * MIB counters RW
+ */
+#define MIB_DOT11_WEP_EXCLUDED_COUNT 0x800
+#define MIB_DOT11_FCS_ERROR_COUNT 0x804
+#define MIB_DOT11_RX_PHY_ERROR_COUNT 0x808
+#define MIB_DOT11_RX_FIFO_OVERFLOW_COUNT 0x80C
+#define MIB_DOT11_TX_UNDERRUN_COUNT 0x810
+#define MIB_RW_QOS_U_TRANSMITTED_MPDU_COUNT_TID0 0x814
+#define MIB_RW_QOS_U_TRANSMITTED_MPDU_COUNT_TID1 0x818
+#define MIB_RW_QOS_U_TRANSMITTED_MPDU_COUNT_TID2 0x81C
+#define MIB_RW_QOS_U_TRANSMITTED_MPDU_COUNT_TID3 0x820
+#define MIB_RW_QOS_U_TRANSMITTED_MPDU_COUNT_TID4 0x824
+#define MIB_RW_QOS_U_TRANSMITTED_MPDU_COUNT_TID5 0x828
+#define MIB_RW_QOS_U_TRANSMITTED_MPDU_COUNT_TID6 0x82C
+#define MIB_RW_QOS_U_TRANSMITTED_MPDU_COUNT_TID7 0x830
+#define MIB_RW_QOS_G_TRANSMITTED_MPDU_COUNT_TID0 0x834
+#define MIB_RW_QOS_G_TRANSMITTED_MPDU_COUNT_TID1 0x838
+#define MIB_RW_QOS_G_TRANSMITTED_MPDU_COUNT_TID2 0x83C
+#define MIB_RW_QOS_G_TRANSMITTED_MPDU_COUNT_TID3 0x840
+#define MIB_RW_QOS_G_TRANSMITTED_MPDU_COUNT_TID4 0x844
+#define MIB_RW_QOS_G_TRANSMITTED_MPDU_COUNT_TID5 0x848
+#define MIB_RW_QOS_G_TRANSMITTED_MPDU_COUNT_TID6 0x84C
+#define MIB_RW_QOS_G_TRANSMITTED_MPDU_COUNT_TID7 0x850
+#define MIB_DOT11_QOS_FAILED_COUNT0 0x854
+#define MIB_DOT11_QOS_FAILED_COUNT1 0x858
+#define MIB_DOT11_QOS_FAILED_COUNT2 0x85C
+#define MIB_DOT11_QOS_FAILED_COUNT3 0x860
+#define MIB_DOT11_QOS_FAILED_COUNT4 0x864
+#define MIB_DOT11_QOS_FAILED_COUNT5 0x868
+#define MIB_DOT11_QOS_FAILED_COUNT6 0x86C
+#define MIB_DOT11_QOS_FAILED_COUNT7 0x870
+#define MIB_DOT11_QOS_RETRY_COUNT0 0x874
+#define MIB_DOT11_QOS_RETRY_COUNT1 0x878
+#define MIB_DOT11_QOS_RETRY_COUNT2 0x87C
+#define MIB_DOT11_QOS_RETRY_COUNT3 0x880
+#define MIB_DOT11_QOS_RETRY_COUNT4 0x884
+#define MIB_DOT11_QOS_RETRY_COUNT5 0x888
+#define MIB_DOT11_QOS_RETRY_COUNT6 0x88C
+#define MIB_DOT11_QOS_RETRY_COUNT7 0x890
+#define MIB_DOT11_QOS_RTS_SUCCESS_COUNT0 0x894
+#define MIB_DOT11_QOS_RTS_SUCCESS_COUNT1 0x898
+#define MIB_DOT11_QOS_RTS_SUCCESS_COUNT2 0x89C
+#define MIB_DOT11_QOS_RTS_SUCCESS_COUNT3 0x8A0
+#define MIB_DOT11_QOS_RTS_SUCCESS_COUNT4 0x8A4
+#define MIB_DOT11_QOS_RTS_SUCCESS_COUNT5 0x8A8
+#define MIB_DOT11_QOS_RTS_SUCCESS_COUNT6 0x8AC
+#define MIB_DOT11_QOS_RTS_SUCCESS_COUNT7 0x8B0
+#define MIB_DOT11_QOS_RTS_FAILURE_COUNT0 0x8B4
+#define MIB_DOT11_QOS_RTS_FAILURE_COUNT1 0x8B8
+#define MIB_DOT11_QOS_RTS_FAILURE_COUNT2 0x8BC
+#define MIB_DOT11_QOS_RTS_FAILURE_COUNT3 0x8C0
+#define MIB_DOT11_QOS_RTS_FAILURE_COUNT4 0x8C4
+#define MIB_DOT11_QOS_RTS_FAILURE_COUNT5 0x8C8
+#define MIB_DOT11_QOS_RTS_FAILURE_COUNT6 0x8CC
+#define MIB_DOT11_QOS_RTS_FAILURE_COUNT7 0x8D0
+#define MIB_RW_QOS_ACK_FAILURE_COUNT0 0x8D4
+#define MIB_RW_QOS_ACK_FAILURE_COUNT1 0x8D8
+#define MIB_RW_QOS_ACK_FAILURE_COUNT2 0x8DC
+#define MIB_RW_QOS_ACK_FAILURE_COUNT3 0x8E0
+#define MIB_RW_QOS_ACK_FAILURE_COUNT4 0x8E4
+#define MIB_RW_QOS_ACK_FAILURE_COUNT5 0x8E8
+#define MIB_RW_QOS_ACK_FAILURE_COUNT6 0x8EC
+#define MIB_RW_QOS_ACK_FAILURE_COUNT7 0x8F0
+#define MIB_RW_QOS_U_RECEIVED_MPDU_COUNT0 0x8F4
+#define MIB_RW_QOS_U_RECEIVED_MPDU_COUNT1 0x8F8
+#define MIB_RW_QOS_U_RECEIVED_MPDU_COUNT2 0x8FC
+#define MIB_RW_QOS_U_RECEIVED_MPDU_COUNT3 0x900
+#define MIB_RW_QOS_U_RECEIVED_MPDU_COUNT4 0x904
+#define MIB_RW_QOS_U_RECEIVED_MPDU_COUNT5 0x908
+#define MIB_RW_QOS_U_RECEIVED_MPDU_COUNT6 0x90C
+#define MIB_RW_QOS_U_RECEIVED_MPDU_COUNT7 0x910
+#define MIB_RW_QOS_G_RECEIVED_MPDU_COUNT0 0x914
+#define MIB_RW_QOS_G_RECEIVED_MPDU_COUNT1 0x918
+#define MIB_RW_QOS_G_RECEIVED_MPDU_COUNT2 0x91C
+#define MIB_RW_QOS_G_RECEIVED_MPDU_COUNT3 0x920
+#define MIB_RW_QOS_G_RECEIVED_MPDU_COUNT4 0x924
+#define MIB_RW_QOS_G_RECEIVED_MPDU_COUNT5 0x928
+#define MIB_RW_QOS_G_RECEIVED_MPDU_COUNT6 0x92C
+#define MIB_RW_QOS_G_RECEIVED_MPDU_COUNT7 0x930
+#define MIB_RW_QOS_U_RECEIVED_OTHER_MPDU0 0x934
+#define MIB_RW_QOS_U_RECEIVED_OTHER_MPDU1 0x938
+#define MIB_RW_QOS_U_RECEIVED_OTHER_MPDU2 0x93C
+#define MIB_RW_QOS_U_RECEIVED_OTHER_MPDU3 0x940
+#define MIB_RW_QOS_U_RECEIVED_OTHER_MPDU4 0x944
+#define MIB_RW_QOS_U_RECEIVED_OTHER_MPDU5 0x948
+#define MIB_RW_QOS_U_RECEIVED_OTHER_MPDU6 0x94C
+#define MIB_RW_QOS_U_RECEIVED_OTHER_MPDU7 0x950
+#define MIB_DOT11_QOS_RETRIES_RECEIVED_COUNT0 0x954
+#define MIB_DOT11_QOS_RETRIES_RECEIVED_COUNT1 0x958
+#define MIB_DOT11_QOS_RETRIES_RECEIVED_COUNT2 0x95C
+#define MIB_DOT11_QOS_RETRIES_RECEIVED_COUNT3 0x960
+#define MIB_DOT11_QOS_RETRIES_RECEIVED_COUNT4 0x964
+#define MIB_DOT11_QOS_RETRIES_RECEIVED_COUNT5 0x968
+#define MIB_DOT11_QOS_RETRIES_RECEIVED_COUNT6 0x96C
+#define MIB_DOT11_QOS_RETRIES_RECEIVED_COUNT7 0x970
+#define MIB_RW_U_TRANSMITTED_AMSDU_COUNT0 0x974
+#define MIB_RW_U_TRANSMITTED_AMSDU_COUNT1 0x978
+#define MIB_RW_U_TRANSMITTED_AMSDU_COUNT2 0x97C
+#define MIB_RW_U_TRANSMITTED_AMSDU_COUNT3 0x980
+#define MIB_RW_U_TRANSMITTED_AMSDU_COUNT4 0x984
+#define MIB_RW_U_TRANSMITTED_AMSDU_COUNT5 0x988
+#define MIB_RW_U_TRANSMITTED_AMSDU_COUNT6 0x98C
+#define MIB_RW_U_TRANSMITTED_AMSDU_COUNT7 0x990
+#define MIB_RW_G_TRANSMITTED_AMSDU_COUNT0 0x994
+#define MIB_RW_G_TRANSMITTED_AMSDU_COUNT1 0x998
+#define MIB_RW_G_TRANSMITTED_AMSDU_COUNT2 0x99C
+#define MIB_RW_G_TRANSMITTED_AMSDU_COUNT3 0x9A0
+#define MIB_RW_G_TRANSMITTED_AMSDU_COUNT4 0x9A4
+#define MIB_RW_G_TRANSMITTED_AMSDU_COUNT5 0x9A8
+#define MIB_RW_G_TRANSMITTED_AMSDU_COUNT6 0x9AC
+#define MIB_RW_G_TRANSMITTED_AMSDU_COUNT7 0x9B0
+#define MIB_DOT11_FAILED_AMSDU_COUNT0 0x9B4
+#define MIB_DOT11_FAILED_AMSDU_COUNT1 0x9B8
+#define MIB_DOT11_FAILED_AMSDU_COUNT2 0x9BC
+#define MIB_DOT11_FAILED_AMSDU_COUNT3 0x9C0
+#define MIB_DOT11_FAILED_AMSDU_COUNT4 0x9C4
+#define MIB_DOT11_FAILED_AMSDU_COUNT5 0x9C8
+#define MIB_DOT11_FAILED_AMSDU_COUNT6 0x9CC
+#define MIB_DOT11_FAILED_AMSDU_COUNT7 0x9D0
+#define MIB_DOT11_RETRY_AMSDU_COUNT0 0x9D4
+#define MIB_DOT11_RETRY_AMSDU_COUNT1 0x9D8
+#define MIB_DOT11_RETRY_AMSDU_COUNT2 0x9DC
+#define MIB_DOT11_RETRY_AMSDU_COUNT3 0x9E0
+#define MIB_DOT11_RETRY_AMSDU_COUNT4 0x9E4
+#define MIB_DOT11_RETRY_AMSDU_COUNT5 0x9E8
+#define MIB_DOT11_RETRY_AMSDU_COUNT6 0x9EC
+#define MIB_DOT11_RETRY_AMSDU_COUNT7 0x9F0
+#define MIB_DOT11_TRANSMITTED_OCTETS_IN_AMSDU0 0x9F4
+#define MIB_DOT11_TRANSMITTED_OCTETS_IN_AMSDU1 0x9F8
+#define MIB_DOT11_TRANSMITTED_OCTETS_IN_AMSDU2 0x9FC
+#define MIB_DOT11_TRANSMITTED_OCTETS_IN_AMSDU3 0xA00
+#define MIB_DOT11_TRANSMITTED_OCTETS_IN_AMSDU4 0xA04
+#define MIB_DOT11_TRANSMITTED_OCTETS_IN_AMSDU5 0xA08
+#define MIB_DOT11_TRANSMITTED_OCTETS_IN_AMSDU6 0xA0C
+#define MIB_DOT11_TRANSMITTED_OCTETS_IN_AMSDU7 0xA10
+#define MIB_DOT11_AMSDU_ACK_FAILURE_COUNT0 0xA14
+#define MIB_DOT11_AMSDU_ACK_FAILURE_COUNT1 0xA18
+#define MIB_DOT11_AMSDU_ACK_FAILURE_COUNT2 0xA1C
+#define MIB_DOT11_AMSDU_ACK_FAILURE_COUNT3 0xA20
+#define MIB_DOT11_AMSDU_ACK_FAILURE_COUNT4 0xA24
+#define MIB_DOT11_AMSDU_ACK_FAILURE_COUNT5 0xA28
+#define MIB_DOT11_AMSDU_ACK_FAILURE_COUNT6 0xA2C
+#define MIB_DOT11_AMSDU_ACK_FAILURE_COUNT7 0xA30
+#define MIB_RW_U_RECEIVED_AMSDU_COUNT0 0xA34
+#define MIB_RW_U_RECEIVED_AMSDU_COUNT1 0xA38
+#define MIB_RW_U_RECEIVED_AMSDU_COUNT2 0xA3C
+#define MIB_RW_U_RECEIVED_AMSDU_COUNT3 0xA40
+#define MIB_RW_U_RECEIVED_AMSDU_COUNT4 0xA44
+#define MIB_RW_U_RECEIVED_AMSDU_COUNT5 0xA48
+#define MIB_RW_U_RECEIVED_AMSDU_COUNT6 0xA4C
+#define MIB_RW_U_RECEIVED_AMSDU_COUNT7 0xA50
+#define MIB_RW_G_RECEIVED_AMSDU_COUNT0 0xA54
+#define MIB_RW_G_RECEIVED_AMSDU_COUNT1 0xA58
+#define MIB_RW_G_RECEIVED_AMSDU_COUNT2 0xA5C
+#define MIB_RW_G_RECEIVED_AMSDU_COUNT3 0xA60
+#define MIB_RW_G_RECEIVED_AMSDU_COUNT4 0xA64
+#define MIB_RW_G_RECEIVED_AMSDU_COUNT5 0xA68
+#define MIB_RW_G_RECEIVED_AMSDU_COUNT6 0xA6C
+#define MIB_RW_G_RECEIVED_AMSDU_COUNT7 0xA70
+#define MIB_RW_U_RECEIVED_OTHER_COUNT0 0xA74
+#define MIB_RW_U_RECEIVED_OTHER_COUNT1 0xA78
+#define MIB_RW_U_RECEIVED_OTHER_COUNT2 0xA7C
+#define MIB_RW_U_RECEIVED_OTHER_COUNT3 0xA80
+#define MIB_RW_U_RECEIVED_OTHER_COUNT4 0xA84
+#define MIB_RW_U_RECEIVED_OTHER_COUNT5 0xA88
+#define MIB_RW_U_RECEIVED_OTHER_COUNT6 0xA8C
+#define MIB_RW_U_RECEIVED_OTHER_COUNT7 0xA90
+#define MIB_DOT11_RECEIVED_OCTETS_IN_AMSDU_COUNT0 0xA94
+#define MIB_DOT11_RECEIVED_OCTETS_IN_AMSDU_COUNT1 0xA98
+#define MIB_DOT11_RECEIVED_OCTETS_IN_AMSDU_COUNT2 0xA9C
+#define MIB_DOT11_RECEIVED_OCTETS_IN_AMSDU_COUNT3 0xAA0
+#define MIB_DOT11_RECEIVED_OCTETS_IN_AMSDU_COUNT4 0xAA4
+#define MIB_DOT11_RECEIVED_OCTETS_IN_AMSDU_COUNT5 0xAA8
+#define MIB_DOT11_RECEIVED_OCTETS_IN_AMSDU_COUNT6 0xAAC
+#define MIB_DOT11_RECEIVED_OCTETS_IN_AMSDU_COUNT7 0xAB0
+
+/* RESERVED 173 - 176 */
+
+#define MIB_DOT11_BEAMFORMING_FRAME_COUNT 0xAC0
+#define BEAMFORMING_RECEIVED_FRAME_COUNT 0xAC4
+#define MIB_RW_SU_BFR_TRANSMITTED_COUNT 0xAC8
+#define MIB_RW_MU_BFR_TRANSMITTED_COUNT 0xACC
+#define MIB_RW_BFR_RECEIVED_COUNT 0xAD0
+#define MIB_RW_MU_RECEIVED_FRAME_COUNT 0xAD4
+
+/* RESERVED 182 - 203 */
+
+#define MIB_DOT11_TRANSMITTED_AMPDU_COUNT 0xB30
+#define MIB_DOT11_TRANSMITTED_MPDUIN_AMPDU_COUNT 0xB34
+#define MIB_DOT11_TRANSMITTED_OCTESTS_IN_AMPDU_COUNT 0xB38
+#define MIB_RW_U_AMPDU_RECEIVED_COUNT 0xB3C
+#define MIB_RW_G_AMPDU_RECEIVED_COUNT 0xB40
+#define MIB_RW_OTHER_AMPDU_RECEIVED_COUNT 0xB44
+#define MIB_DOT11_MPDU_IN_RECEIVED_AMPDU_COUNT 0xB48
+#define MIB_DOT11_RECEIVED_OCTETS_IN_AMPDU_COUNT 0xB4C
+#define MIB_DOT11_AMPDU_DELIMITER_CRC_ERROR_COUNT 0xB50
+#define MIB_DOT11_IMPLICIT_BAR_FAILURE_COUNT 0xB54
+#define MIB_DOT11_EXPLICIT_BAR_FAILURE_COUNT 0xB58
+
+/* RESERVED  215-219 */
+
+#define MIB_DOT11_20MHZ_FRAME_TRANSMITTED_COUNT 0xB70
+#define MIB_DOT11_40MHZ_FRAME_TRANSMITTED_COUNT 0xB74
+#define MIB_DOT11_80MHZ_FRAME_TRANSMITTED_COUNT 0xB78
+#define MIB_DOT11_160MHZ_FRAME_TRANSMITTED_COUNT 0xB7C
+#define MIB_DOT11_20MHZ_FRAME_RECEIVED_COUNT 0xB80
+#define MIB_DOT11_40MHZ_FRAME_RECEIVED_COUNT 0xB84
+#define MIB_DOT11_80MHZ_FRAME_RECEIVED_COUNT 0xB88
+#define MIB_DOT11_160MHZ_FRAME_RECEIVED_COUNT 0xB8C
+#define MIB_RW_20MHZ_FAILED_TXOP_COUNT 0xB90
+#define MIB_RW_20MHZ_SUCCESSFUL_TXOP_COUNT 0xB94
+#define MIB_RW_40MHZ_FAILED_TXOP_COUNT 0xB98
+#define MIB_RW_40MHZ_SUCCESSFUL_TXOP_COUNT 0xB9C
+#define MIB_RW_80MHZ_FAILED_TXOP_COUNT 0xBA0
+#define MIB_RW_80MHZ_SUCCESSFUL_TXOP_COUNT 0xBA4
+#define MIB_RW_160MHZ_FAILED_TXOP_COUNT 0xBA8
+#define MIB_RW_160MHZ_SUCCESSFUL_TXOP_COUNT 0xBAC
+#define MIB_RW_DYN_BW_DROP_COUNT 0xBB0
+#define MIB_RW_STA_BW_FAILED_COUNT 0xBB4
+
+/* RESERVED 238-239 */
+
+#define MIB_DOT11_DUAL_CTS_SUCCESS_COUNT 0xBC0
+#define MIB_DOT11_STBC_CTS_SUCCESS_COUNT 0xBC4
+#define MIB_DOT11_STBC_CTS_FAILURE_COUNT 0xBC8
+#define MIB_DOT11_NON_STBC_CTS_SUCCESS_COUNT 0xBCC
+#define MIB_DOT11_NON_STBC_CTS_FAILURE_COUNT 0xBD0
+
+/*
+ * MIB counters Celeno
+ */
+#define MIB_TX_UND_DISCARD_FCS_COUNT 0xBD4
+#define MIB_AMPDU_INCORRECT_RCVED_COUNT 0xBD8
+#define MIB_CL_RX_CLASS0_MATCH_COUNT 0xBDC
+#define MIB_CL_RX_CLASS1_MATCH_COUNT 0xBE0
+#define MIB_CL_RX_CLASS2_MATCH_COUNT 0xBE4
+#define MIB_CL_RX_CLASS3_MATCH_COUNT 0xBE8
+#define MIB_CL_RX_CLASS4_MATCH_COUNT 0xBEC
+#define MIB_CL_RX_CLASS5_MATCH_COUNT 0xBF0
+#define MIB_RW_RX_MPIF_OVERFLOW_COUNT 0xBF4
+
+#define MIB_RESP_SET_BY_FW 0xAD8
+#define MIB_RESP_FORCE_BY_FW 0xADC
+#define MIB_RESP_SET_BY_HW 0xAE0
+#define MIB_RESP_FORCED_BY_HW 0xAE4
+#define MIB_RX_UNEXPECTED_FRAME_TYPE_IN_AMPDU 0xAE8
+#define MIB_RX_MILTI_TID 0xAEC
+#define MIB_KSR_MISS_QOS_DATA_IN_AMPDU 0xAF0
+#define MIB_KSR_MISS_MULTI_TID 0xAF4
+#define MIB_KSR_MISS_QOS_DATA_IN_AMPDUHE_TB 0xAF8
+#define MIB_RX_UNASSOCIATED_MGMT_IN_HE_TB 0xAFC
+#define MIB_HTP_FAILED_MEDIUM_CHECK_COUNT 0xB00
+#define MIB_RX_ERROR_VECTOR0 0xB04
+#define MIB_RX_ERROR_VECTOR1 0xB08
+#define MIB_RX_ERROR_VECTOR2 0xB0C
+#define MIB_RX_ERROR_VECTOR3 0xB10
+#define MIB_RX_ERROR_VECTOR4 0xB14
+#define MIB_RX_ERROR_VECTOR5 0xB18
+#define MIB_RX_ERROR_VECTOR6 0xB1C
+#define MIB_RX_ERROR_VECTOR7 0xB20
+#define MIB_RX_ERROR_VECTOR8 0xB24
+#define MIB_RX_ERROR_VECTOR9 0xB28
+#define MIB_RX_ERROR_VECTOR10 0xB2C
+#define MIB_RX_ERROR_VECTOR11 0xB5C
+#define MIB_RX_ERROR_VECTOR12 0xB60
+#define MIB_RX_ERROR_VECTOR13 0xB64
+#define MIB_RX_ERROR_VECTOR14 0xB68
+#define MIB_RX_ERROR_VECTOR15 0xB6C
+
+void cl_mib_cntrs_dump(struct cl_hw *cl_hw);
+u32 cl_mib_cntr_read(struct cl_hw *cl_hw, u32 addr);
+
+#endif /* CL_MIB_H */