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[RFC,v1,158/256] cl8k: add reg/reg_macsys_gcu.h

Message ID 20210617160223.160998-159-viktor.barna@celeno.com (mailing list archive)
State RFC
Delegated to: Kalle Valo
Headers show
Series wireless: cl8k driver for Celeno IEEE 802.11ax devices | expand

Commit Message

Viktor Barna June 17, 2021, 4 p.m. UTC
From: Viktor Barna <viktor.barna@celeno.com>

(Part of the split. Please, take a look at the cover letter for more
details).

Signed-off-by: Viktor Barna <viktor.barna@celeno.com>
---
 .../wireless/celeno/cl8k/reg/reg_macsys_gcu.h | 94 +++++++++++++++++++
 1 file changed, 94 insertions(+)
 create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_macsys_gcu.h

--
2.30.0
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Patch

diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_macsys_gcu.h b/drivers/net/wireless/celeno/cl8k/reg/reg_macsys_gcu.h
new file mode 100644
index 000000000000..41eb196f4b7c
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/reg/reg_macsys_gcu.h
@@ -0,0 +1,94 @@ 
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_REG_MACSYS_GCU_H
+#define CL_REG_MACSYS_GCU_H
+
+#include <linux/types.h>
+#include "reg/reg_access.h"
+#include "chip.h"
+
+#define REG_MACSYS_GCU_BASE_ADDR 0x007C5000
+#define REG_MACSYS_GCU_COUNT 63
+
+/*
+ * @brief CHIP_VERSION register definition
+ * Chip Version 8000B0 register description
+ * <pre>
+ * Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *  23:08 PRODUCT_ID                0x8000
+ *  07:04 STEP_ID                   0xB
+ *  03:00 REV_ID                    0x0
+ * </pre>
+ */
+#define MACSYS_GCU_CHIP_VERSION_ADDR        (REG_MACSYS_GCU_BASE_ADDR + 0x00000050)
+#define MACSYS_GCU_CHIP_VERSION_OFFSET      0x00000050
+#define MACSYS_GCU_CHIP_VERSION_INDEX       0x00000014
+#define MACSYS_GCU_CHIP_VERSION_RESET       0x008000B0
+
+static inline u32 macsys_gcu_chip_version_get(struct cl_chip *chip)
+{
+       return cl_reg_read_chip(chip, MACSYS_GCU_CHIP_VERSION_ADDR);
+}
+
+/* Field definitions */
+#define MACSYS_GCU_CHIP_VERSION_PRODUCT_ID_MASK  ((u32)0x00FFFF00)
+#define MACSYS_GCU_CHIP_VERSION_PRODUCT_ID_LSB   8
+#define MACSYS_GCU_CHIP_VERSION_PRODUCT_ID_WIDTH ((u32)0x00000010)
+#define MACSYS_GCU_CHIP_VERSION_STEP_ID_MASK     ((u32)0x000000F0)
+#define MACSYS_GCU_CHIP_VERSION_STEP_ID_LSB      4
+#define MACSYS_GCU_CHIP_VERSION_STEP_ID_WIDTH    ((u32)0x00000004)
+#define MACSYS_GCU_CHIP_VERSION_REV_ID_MASK      ((u32)0x0000000F)
+#define MACSYS_GCU_CHIP_VERSION_REV_ID_LSB       0
+#define MACSYS_GCU_CHIP_VERSION_REV_ID_WIDTH     ((u32)0x00000004)
+
+static inline u8 macsys_gcu_chip_version_step_id_getf(struct cl_chip *chip)
+{
+       u32 local_val = cl_reg_read_chip(chip, MACSYS_GCU_CHIP_VERSION_ADDR);
+
+       return ((local_val & ((u32)0x000000F0)) >> 4);
+}
+
+/*
+ * @brief XT_CONTROL register definition
+ * Tensilica control register description
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ * -----   ------------------   -----------
+ *   21    smac_debug_en             0
+ *   20    smac_break_in             0
+ *   19    smac_ocd_halt_on_reset    1
+ *   18    smac_run_stall            0
+ *   17    smac_dreset_n             1
+ *   16    smac_breset_n             0
+ *   13    umac_debug_en             0
+ *   12    umac_break_in             0
+ *   11    umac_ocd_halt_on_reset    1
+ *   10    umac_run_stall            0
+ *   09    umac_dreset_n             1
+ *   08    umac_breset_n             0
+ *   05    lmac_debug_en             0
+ *   04    lmac_break_in             0
+ *   03    lmac_ocd_halt_on_reset    1
+ *   02    lmac_run_stall            0
+ *   01    lmac_dreset_n             1
+ *   00    lmac_breset_n             0
+ * </pre>
+ */
+#define MACSYS_GCU_XT_CONTROL_ADDR        (REG_MACSYS_GCU_BASE_ADDR + 0x000000F0)
+#define MACSYS_GCU_XT_CONTROL_OFFSET      0x000000F0
+#define MACSYS_GCU_XT_CONTROL_INDEX       0x0000003C
+#define MACSYS_GCU_XT_CONTROL_RESET       0x000A0A0A
+
+static inline u32 macsys_gcu_xt_control_get(struct cl_chip *chip)
+{
+       return cl_reg_read_chip(chip, MACSYS_GCU_XT_CONTROL_ADDR);
+}
+
+static inline void macsys_gcu_xt_control_set(struct cl_chip *chip, u32 value)
+{
+       cl_reg_write_chip(chip, MACSYS_GCU_XT_CONTROL_ADDR, value);
+}
+
+#endif /* CL_REG_MACSYS_GCU_H */