new file mode 100644
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_AGC_PARAMS_H
+#define CL_AGC_PARAMS_H
+
+#include <linux/types.h>
+#include <linux/bitfield.h>
+#include "def.h"
+#include "vendor_cmd.h"
+
+/**
+ * AGC (=Automatic Gain Control)
+ */
+
+/* AGC PROFILE */
+#define AGC_PROFILE_BAND_OFFSET 28
+#define AGC_PROFILE_BAND_MASK 0xf0000000
+#define AGC_PROFILE_BRANCH_OFFSET 20
+#define AGC_PROFILE_BRANCH_MASK 0x0ff00000
+#define AGC_PROFILE_VERSION_OFFSET 12
+#define AGC_PROFILE_VERSION_MASK 0x000ff000
+#define AGC_PROFILE_RESERVED_OFFSET 0
+#define AGC_PROFILE_RESERVED_MASK 0x00000fff
+
+#define AGC_PROFILE(band, branch, version) \
+ (((band) << AGC_PROFILE_BAND_OFFSET) | \
+ ((branch) << AGC_PROFILE_BRANCH_OFFSET) | \
+ ((version) << AGC_PROFILE_VERSION_OFFSET))
+
+#define AGC_PROFILE_BAND(profile) \
+ u32_get_bits(profile, AGC_PROFILE_BAND_MASK)
+#define AGC_PROFILE_BRANCH(profile) \
+ u32_get_bits(profile, AGC_PROFILE_BRANCH_MASK)
+#define AGC_PROFILE_VERSION(profile) \
+ u32_get_bits(profile, AGC_PROFILE_VERSION_MASK)
+
+/* AGC PLATFORM */
+#define AGC_PLATFORM_CUSTOMER_OFFSET 16
+#define AGC_PLATFORM_CUSTOMER_MASK 0xffff0000
+#define AGC_PLATFORM_BOARD_OFFSET 8
+#define AGC_PLATFORM_BOARD_MASK 0x0000ff00
+#define AGC_PLATFORM_CHIP_OFFSET 4
+#define AGC_PLATFORM_CHIP_MASK 0x000000f0
+#define AGC_PLATFORM_RESERVED_OFFSET 0
+#define AGC_PLATFORM_RESERVED_MASK 0x0000000f
+
+#define AGC_PLATFORM(customer, board, chip) \
+ (((customer) << AGC_PLATFORM_CUSTOMER_OFFSET) | \
+ ((board) << AGC_PLATFORM_BOARD_OFFSET) | \
+ ((chip) << AGC_PLATFORM_CHIP_OFFSET))
+
+#define AGC_PLATFORM_CUSTOMER(platform) \
+ u32_get_bits(platform, AGC_PLATFORM_CUSTOMER_MASK)
+#define AGC_PLATFORM_BOARD(platform) \
+ u32_get_bits(platform, AGC_PLATFORM_BOARD_MASK)
+#define AGC_PLATFORM_CHIP(platform) \
+ u32_get_bits(platform, AGC_PLATFORM_CHIP_MASK)
+
+enum cl_customer_list {
+ CL_CUSTOMER_CELENO = 0,
+};
+
+enum cl_board_list {
+ /* Board list for Celeno customer */
+ CL_BOARD_EVB = 0,
+ /* Values from 1 to 5 are reserved */
+ CL_BOARD_MERLIN = 6,
+ CL_BOARD_EVB_6G = 7,
+ CL_BOARD_ALBATROSS = 8,
+ CL_BOARD_ALBATROSS_2 = 9,
+ CL_BOARD_CHAMELEON = 10,
+};
+
+struct cl_agc_reg {
+ u32 val;
+ u32 mask;
+};
+
+struct cl_agc_profile {
+ u32 id;
+ struct cl_agc_reg fsm_preset_p2; /* 0x244 */
+ struct cl_agc_reg lna_thr_set0_ref2; /* 0x25C */
+ struct cl_agc_reg lna_thr_set0_ref3; /* 0x260 */
+ struct cl_agc_reg lna_thr_set1_ref2; /* 0x264 */
+ struct cl_agc_reg lna_thr_set1_ref3; /* 0x268 */
+ struct cl_agc_reg lna_thr_set2_ref2; /* 0x26C */
+ struct cl_agc_reg lna_thr_set2_ref3; /* 0x270 */
+ struct cl_agc_reg lna_gain_set0_ref2; /* 0x274 */
+ struct cl_agc_reg lna_gain_set0_ref3; /* 0x278 */
+ struct cl_agc_reg lna_nf_set0_ref2; /* 0x27C */
+ struct cl_agc_reg lna_nf_set0_ref3; /* 0x280 */
+ struct cl_agc_reg lna_icp1_set0_ref2; /* 0x284 */
+ struct cl_agc_reg lna_icp1_set0_ref3; /* 0x288 */
+ struct cl_agc_reg fsm_preset_p10; /* 0x2A8 */
+ struct cl_agc_reg fsm_preset_p11; /* 0x2AC */
+ struct cl_agc_reg fsm_preset_p12; /* 0x2B0 */
+ struct cl_agc_reg ant_loss; /* 0x300 */
+ struct cl_agc_reg gain_range; /* 0x304 */
+ struct cl_agc_reg vga_ref0; /* 0x308 */
+ struct cl_agc_reg lna_gain_set0_ref0; /* 0x30C */
+ struct cl_agc_reg lna_gain_set0_ref1; /* 0x310 */
+ struct cl_agc_reg lna_thr_set0_ref0; /* 0x314 */
+ struct cl_agc_reg lna_thr_set0_ref1; /* 0x318 */
+ struct cl_agc_reg lna_thr_set1_ref0; /* 0x31C */
+ struct cl_agc_reg lna_thr_set1_ref1; /* 0x320 */
+ struct cl_agc_reg lna_thr_set2_ref0; /* 0x324 */
+ struct cl_agc_reg lna_thr_set2_ref1; /* 0x328 */
+ struct cl_agc_reg lna_nf_set0_ref0; /* 0x32C */
+ struct cl_agc_reg lna_nf_set0_ref1; /* 0x330 */
+ struct cl_agc_reg lna_icp1_set0_ref0; /* 0x334 */
+ struct cl_agc_reg lna_icp1_set0_ref1; /* 0x338 */
+ struct cl_agc_reg saturation; /* 0x364 */
+ struct cl_agc_reg ramp; /* 0x36C */
+ struct cl_agc_reg dsp0; /* 0x394 */
+ struct cl_agc_reg dsp1; /* 0x398 */
+ struct cl_agc_reg dsp2; /* 0x39C */
+ struct cl_agc_reg dsp3; /* 0x3A0 */
+ struct cl_agc_reg lna_gain_set1_ref0; /* 0x590 */
+ struct cl_agc_reg lna_gain_set1_ref1; /* 0x594 */
+ struct cl_agc_reg lna_gain_set1_ref2; /* 0x598 */
+ struct cl_agc_reg lna_gain_set1_ref3; /* 0x59c */
+ struct cl_agc_reg lna_nf_set1_ref0; /* 0x5A0 */
+ struct cl_agc_reg lna_nf_set1_ref1; /* 0x5A4 */
+ struct cl_agc_reg lna_nf_set1_ref2; /* 0x5A8 */
+ struct cl_agc_reg lna_nf_set1_ref3 ; /* 0x5AC */
+ struct cl_agc_reg lna_icp1_set1_ref0; /* 0x5B0 */
+ struct cl_agc_reg lna_icp1_set1_ref1; /* 0x5B4 */
+ struct cl_agc_reg lna_icp1_set1_ref2; /* 0x5B8 */
+ struct cl_agc_reg lna_icp1_set1_ref3 ;/* 0x5BC */
+};
+
+struct cl_agc_params {
+ u8 num_profiles;
+ u8 ant_mask1;
+ u8 ant_mask2;
+ struct cl_agc_profile profile1;
+ struct cl_agc_profile profile2;
+};
+
+struct cl_chip;
+struct cl_hw;
+
+int cl_agc_params_read_platform_id(struct cl_chip *chip);
+int cl_agc_params_fill(struct cl_hw *cl_hw, struct cl_agc_params *agc_params);
+void cl_agc_params_print_profile(char **buf, int *len, ssize_t *buf_size,
+ struct cl_agc_profile *profile,
+ const char *str);
+int cl_agc_params_cli(struct cl_hw *cl_hw, struct cli_params *cli_params);
+
+#endif /* CL_AGC_PARAMS_H */