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[RFC,v1,134/256] cl8k: add power.h

Message ID 20210617160223.160998-135-viktor.barna@celeno.com (mailing list archive)
State RFC
Delegated to: Kalle Valo
Headers show
Series wireless: cl8k driver for Celeno IEEE 802.11ax devices | expand

Commit Message

Viktor Barna June 17, 2021, 4 p.m. UTC 
From: Viktor Barna <viktor.barna@celeno.com>

(Part of the split. Please, take a look at the cover letter for more
details).

Signed-off-by: Viktor Barna <viktor.barna@celeno.com>
---
 drivers/net/wireless/celeno/cl8k/power.h | 37 ++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 drivers/net/wireless/celeno/cl8k/power.h

--
2.30.0
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Patch

diff --git a/drivers/net/wireless/celeno/cl8k/power.h b/drivers/net/wireless/celeno/cl8k/power.h
new file mode 100644
index 000000000000..3dc12d618c7c
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/power.h
@@ -0,0 +1,37 @@ 
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_POWER_H
+#define CL_POWER_H
+
+#include "hw.h"
+
+#define POWER_MAX_DB 30
+#define POWER_MIN_DB -10
+
+#define POWER_MIN_DB_Q1 (POWER_MIN_DB << 1)
+#define POWER_MIN_DB_Q8 (POWER_MIN_DB << 8)
+
+#define POWER_OFFSET_RES 4
+
+#define POWER_OFFSET_MAX_Q2 (16 << 2)  /* +16dB * 4 */
+#define POWER_OFFSET_MIN_Q2 (-16 << 2) /* -16dB * 4 */
+
+u8 cl_power_tx_ant(struct cl_hw *cl_hw, enum cl_wrs_mode mode);
+s32 cl_power_antenna_gain_q8(struct cl_hw *cl_hw);
+s32 cl_power_antenna_gain_q1(struct cl_hw *cl_hw);
+s32 cl_power_array_gain_q8(struct cl_hw *cl_hw, u8 tx_ant);
+s8 cl_power_array_gain_q2(struct cl_hw *cl_hw, u8 tx_ant);
+s32 cl_power_array_gain_q1(struct cl_hw *cl_hw, u8 tx_ant);
+s32 cl_power_bf_gain_q1(struct cl_hw *cl_hw, u8 tx_ant, u8 nss);
+s32 cl_power_min_ant_q1(struct cl_hw *cl_hw);
+s8 cl_power_bw_factor_q2(struct cl_hw *cl_hw, u8 bw);
+s32 cl_power_average_calib_q1(struct cl_hw *cl_hw, u8 ant_num);
+s32 cl_power_total_q1(struct cl_hw *cl_hw, s8 pwr_offset_q1, u8 tx_ant, u8 nss,
+                     enum cl_wrs_mode mode, bool is_auto_resp);
+s8 cl_power_offset_q1(struct cl_hw *cl_hw, u8 mode, u8 bw, u8 mcs);
+s8 cl_power_offset_check_margin(struct cl_hw *cl_hw, u8 bw, u8 ant_idx, s8 offset_q2);
+void cl_power_tables_update(struct cl_hw *cl_hw, struct cl_pwr_tables *pwr_tables);
+s32 cl_power_get_max(struct cl_hw *cl_hw);
+
+#endif /* CL_POWER_H */