new file mode 100644
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_REG_LCU_PHY_H
+#define CL_REG_LCU_PHY_H
+
+#include <linux/types.h>
+#include "reg/reg_access.h"
+#include "hw.h"
+
+#define REG_LCU_PHY_BASE_ADDR 0x0048E000
+
+/*
+ * @brief LCU_CH_0_STOP register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 00 CH0_STOP 0
+ * </pre>
+ */
+#define LCU_PHY_LCU_CH_0_STOP_ADDR (REG_LCU_PHY_BASE_ADDR + 0x00000070)
+#define LCU_PHY_LCU_CH_0_STOP_OFFSET 0x00000070
+#define LCU_PHY_LCU_CH_0_STOP_INDEX 0x0000001C
+#define LCU_PHY_LCU_CH_0_STOP_RESET 0x00000000
+
+static inline void lcu_phy_lcu_ch_0_stop_set(struct cl_hw *cl_hw, u32 value)
+{
+ cl_reg_write(cl_hw, LCU_PHY_LCU_CH_0_STOP_ADDR, value);
+}
+
+/* Field definitions */
+#define LCU_PHY_CH_0_STOP_BIT ((u32)0x00000001)
+#define LCU_PHY_CH_0_STOP_POS 0
+
+#define LCU_PHY_CH_0_STOP_RST 0x0
+
+static inline void lcu_phy_lcu_ch_0_stop_ch_0_stop_setf(struct cl_hw *cl_hw, u8 ch0stop)
+{
+ ASSERT_ERR((((u32)ch0stop << 0) & ~((u32)0x00000001)) == 0);
+ cl_reg_write(cl_hw, LCU_PHY_LCU_CH_0_STOP_ADDR, (u32)ch0stop << 0);
+}
+
+/*
+ * @brief LCU_CH_1_STOP register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 00 CH1_STOP 0
+ * </pre>
+ */
+#define LCU_PHY_LCU_CH_1_STOP_ADDR (REG_LCU_PHY_BASE_ADDR + 0x00000074)
+#define LCU_PHY_LCU_CH_1_STOP_OFFSET 0x00000074
+#define LCU_PHY_LCU_CH_1_STOP_INDEX 0x0000001D
+#define LCU_PHY_LCU_CH_1_STOP_RESET 0x00000000
+
+static inline void lcu_phy_lcu_ch_1_stop_set(struct cl_hw *cl_hw, u32 value)
+{
+ cl_reg_write(cl_hw, LCU_PHY_LCU_CH_1_STOP_ADDR, value);
+}
+
+/* Field definitions */
+#define LCU_PHY_CH_1_STOP_BIT ((u32)0x00000001)
+#define LCU_PHY_CH_1_STOP_POS 0
+
+#define LCU_PHY_CH_1_STOP_RST 0x0
+
+static inline void lcu_phy_lcu_ch_1_stop_ch_1_stop_setf(struct cl_hw *cl_hw, u8 ch1stop)
+{
+ ASSERT_ERR((((u32)ch1stop << 0) & ~((u32)0x00000001)) == 0);
+ cl_reg_write(cl_hw, LCU_PHY_LCU_CH_1_STOP_ADDR, (u32)ch1stop << 0);
+}
+
+/*
+ * @brief LCU_SW_RST register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 00 SW_RST 0
+ * </pre>
+ */
+
+#define LCU_PHY_LCU_SW_RST_ADDR (REG_LCU_PHY_BASE_ADDR + 0x00000154)
+#define LCU_PHY_LCU_SW_RST_OFFSET 0x00000154
+#define LCU_PHY_LCU_SW_RST_INDEX 0x00000055
+#define LCU_PHY_LCU_SW_RST_RESET 0x00000000
+
+static inline void lcu_phy_lcu_sw_rst_set(struct cl_hw *cl_hw, u32 value)
+{
+ cl_reg_write(cl_hw, LCU_PHY_LCU_SW_RST_ADDR, value);
+}
+
+#endif /* CL_REG_LCU_PHY_H */