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[RFC,v1,045/256] cl8k: add chip_config.h

Message ID 20210617160223.160998-46-viktor.barna@celeno.com (mailing list archive)
State RFC
Delegated to: Kalle Valo
Headers show
Series wireless: cl8k driver for Celeno IEEE 802.11ax devices | expand

Commit Message

Viktor Barna June 17, 2021, 3:58 p.m. UTC 
From: Viktor Barna <viktor.barna@celeno.com>

(Part of the split. Please, take a look at the cover letter for more
details).

Signed-off-by: Viktor Barna <viktor.barna@celeno.com>
---
 .../net/wireless/celeno/cl8k/chip_config.h    | 58 +++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 drivers/net/wireless/celeno/cl8k/chip_config.h

--
2.30.0
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Patch

diff --git a/drivers/net/wireless/celeno/cl8k/chip_config.h b/drivers/net/wireless/celeno/cl8k/chip_config.h
new file mode 100644
index 000000000000..2cfa20522e0d
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/chip_config.h
@@ -0,0 +1,58 @@ 
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_CHIP_CONFIG_H
+#define CL_CHIP_CONFIG_H
+
+#include "def.h"
+#include "utils/string.h"
+#include <linux/types.h>
+#include <linux/if_ether.h>
+
+#define CC_MAX_LEN 3 /* 2 characters + null */
+#define FW_MAX_NAME 32
+
+struct cl_chip_conf {
+       bool ce_tcv_enabled[TCV_MAX];
+       s8 ce_lmac[FW_MAX_NAME];
+       s8 ce_smac[FW_MAX_NAME];
+       s8 ce_umac[FW_MAX_NAME];
+       s32 ce_irq_smp_affinity;
+       u8 ce_eeprom_mode;
+       bool ce_production_mode;
+       bool ci_pci_msi_enable;
+       u8 ci_dma_lli_max_chan[TCV_MAX];
+       s8 ce_country_code[CC_MAX_LEN];
+       s8 ce_ela_mode[STR_LEN_64B];
+       u8 ci_phy_dev;
+       s8 ce_debug_level;
+       u8 ce_host_pci_gen_ver;
+       bool ce_temp_comp_en;
+       u8 ce_temp_protect_en;
+       s8 ce_temp_protect_delta;
+       s16 ce_temp_protect_th_max;
+       s16 ce_temp_protect_th_min;
+       u16 ce_temp_protect_tx_period_ms;
+       s16 ce_temp_protect_radio_off_th;
+       u8 ce_phys_mac_addr[ETH_ALEN];
+       bool ce_lam_enable;
+       u8 ce_first_mask_bit;
+       bool ci_no_capture_noise_sleep;
+       u8 ci_dcoc_mv_thr[CHNL_BW_MAX];
+       s8 ci_lolc_db_thr;
+       s8 ci_iq_db_thr;
+       bool ci_rx_resched_tasklet;
+       u32 ci_rx_skb_max;
+       bool ce_calib_scan_en;
+
+       /* New NVRAM parameters must be added to cl_chip_config_print() */
+};
+
+struct cl_chip;
+
+int cl_chip_config_read(struct cl_chip *chip);
+int cl_chip_config_set(struct cl_chip *chip, char *buf, loff_t size);
+void cl_chip_config_dealloc(struct cl_chip *chip);
+void cl_chip_config_print(struct cl_chip *chip);
+
+#endif /* CL_CHIP_CONFIG_H */